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cy7c64713 ez-usb fx1? usb microcontroller full speed usb peripheral controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-08039 rev. *l revised march 9, 2014 ez-usb fx1? usb microcontroller full speed usb peripheral controller features single chip integrated usb transceiver, sie, and enhanced 8051 microprocessor fit, form, and function upgradable to the fx2lp (cy7c68013a) ? pin compatible ? object code compatible ? functionally compatible (fx1 functionality is a subset of the fx2lp) draws no more than 65 ma in any mode, making the fx1 suitable for bus powered applications software: 8051 runs from internal ram, which is: ? downloaded using usb ? loaded from eeprom ? external memory device (128 pin configuration only) 16 kb of on-chip code/data ram four programmable bulk/interrupt/isochronous endpoints ? buffering options: double, triple, and quad additional programmable (bulk/interrupt) 64-byte endpoint 8- or 16-bit external data interface smart media standard ecc generation gpif ? allows direct connection to most parallel interfaces; 8- and 16-bit ? programmable waveform descriptors and configuration registers to define waveforms ? supports multiple ready (rdy) inputs and control (ctl) outputs integrated, industry standar d 8051 with enhanced features: ? up to 48 mhz clock rate ? four clocks for each instruction cycle ? two usarts ? three counters or timers ? expanded interrupt system ? two data pointers 3.3 v operation with 5 v tolerant inputs smart sie vectored usb interrupts separate data buffers for the setup and data portions of a control transfer integrated i 2 c controller, running at 100 or 400 khz 48 mhz, 24 mhz, or 12 mhz 8051 operation four integrated fifos ? brings glue and fifos in side for lower system cost ? automatic conversion to and from 16-bit buses ? master or slave operation ? fifos can use externally supplied clock or asynchronous strobes ? easy interface to asic and dsp ics vectored for fifo and gpif interrupts up to 40 general purpose ios (gpio) four package options: ? 128-pin tqfp ? 100-pin tqfp ? 56-pin ssop ? 56-pin qfn pb-free errata: for information on silicon errata, see ?errata? on page 71. details include trigger conditions, devices affected, and proposed workaround.
cy7c64713 document number: 38-08039 rev. *l page 2 of 74 address (16) x20 pll /0.5 /1.0 /2.0 8051 core 12/24/48 mhz, four clocks/cycle i 2 c vcc 1.5k d+ d? address (16) / data bus (8) fx1 gpif cy smart usb engine usb xcvr 16 kb ram 4 kb fifo integrated full speed xcvr additional ios (24) addr (9) ctl (6) rdy (6) 8/16 data (8) 24 mhz ext. xtal enhanced usb core simplifies 8051 code ?soft configuration? easy firmware changes fifo and endpoint memory (master or slave operation) up to 96 mbytes burst rate general programmable i/f to asic/dsp or bus standards such as atapi, epp, etc. abundant i/o including two usarts high performance micro using standard tools with lower-power options master connected for enumeration ecc logic block diagram
cy7c64713 document number: 38-08039 rev. *l page 3 of 74 contents functional description ..................................................... 4 applications ...................................................................... 4 functional overview ........................................................ 4 usb signaling speed ............. .............. .............. ......... 4 8051 microprocessor ... .............. .............. ........... ......... 4 i 2 c bus ........................................................................ 5 buses .......................................................................... 5 usb boot methods ...................................................... 5 renumeration? ..................... ..................................... 6 bus-powered applications ... ........................................ 6 interrupt system .......................................................... 6 reset and wakeup ...................................................... 8 program/data ram ..................................................... 9 endpoint ram ........................................................... 11 external fifo interface ............................................. 11 gpif .......................................................................... 12 ecc generation ........................................................ 13 usb uploads and downloads ... .............. ........... ....... 13 autopointer access ................................................... 13 i 2 c controller ............................................................. 13 compatible with previous generation ez-usb fx2 ..................................................................... 14 pin assignments ............................................................ 14 cy7c64713 pin definitions ............................................ 20 register summary .......................................................... 28 absolute maximum ratings .......................................... 47 operating conditions ..................................................... 47 dc characteristics ......................................................... 47 usb transceiver ....................................................... 47 ac electrical characteristics ........................................ 48 usb transceiver ....................................................... 48 portc strobe feature timings ............................... 51 gpif synchronous signals ....................................... 52 slave fifo synchronous read ................................. 53 slave fifo asynchronous r ead ............ ........... ........ 54 slave fifo synchronous write ................................. 55 slave fifo asynchronous write ............................... 56 slave fifo synchronous pack et end strobe ........... 56 slave fifo asynchronous packet end strobe ......... 58 slave fifo output enable ........................................ 58 slave fifo address to flags/data ............................ 58 slave fifo synchronous address ............................ 59 slave fifo asynchronous address .......................... 59 sequence diagram .................................................... 60 ordering information ...................................................... 64 ordering code definitions ..... .................................... 64 package diagrams .......................................................... 65 quad flat package no leads (qfn) package design notes ................................................................... 68 acronyms ........................................................................ 70 document conventions ................................................. 70 units of measure ....................................................... 70 errata ............................................................................... 71 part numbers affected .............................................. 71 ez-usb fx1 qualification status .............................. 71 ez-usb fx1 errata summary .................................. 71 document history page ................................................. 72 sales, solutions, and legal information ...................... 74 worldwide sales and design s upport ......... .............. 74 products .................................................................... 74 psoc? solutions ...................................................... 74 cypress developer community ................................. 74 technical support ................. .................................... 74
cy7c64713 document number: 38-08039 rev. *l page 4 of 74 functional description ez-usb fx1 ? (cy7c64713) is a full speed, highly integrated, usb microcontroller. by integrating the usb transceiver, serial interface engine (sie), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, cypress has created a very cost effective solution that provides superior time-to-market advantages. the ez-usb fx1 is more economical, because it incorporates the usb transceiver and provides a smaller footprint solution than the usb sie or external tr ansceiver implementations. with ez-usb fx1, the cypress smart sie handles most of the usb protocol in hardware, freeing the embedded microcontroller for application specific functions and decreasing the development time to ensure usb compatibility. the general programmable interf ace (gpif) and master/slave endpoint fifo (8 or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as ata, utopia, epp, pcmcia, and most dsp/processors. four pb-free packages are defined for the family: 56-pin ssop, 56-pin qfn, 100-pin tqfp, and 128-pin tqfp. applications dsl modems ata interface memory card readers legacy conversion devices home pna wireless lan mp3 players networking the reference designs section of the cypress website provides additional tools for typical usb applications. each reference design comes complete with firmware source and object code, schematics, and documentation. please visit http://www.cypress.com for more information. functional overview usb signaling speed fx1 operates at one of the th ree rates defined in the usb specification revision 2.0, dated april 27, 2000: full speed, with a signaling bit rate of 12 mbps. fx1 does not support the low s peed signaling mode of 1.5 mbps or the high speed mode of 480 mbps. 8051 microprocessor the 8051 microprocessor embedded in the fx1 family has 256 bytes of register ram, an expanded interrupt system, three timer/counters, and two usarts. 8051 clock frequency fx1 has an on-chip oscillator circuit that uses an external 24 mhz (100 ppm) crystal with the following characteristics: parallel resonant fundamental mode 500 ? w drive level 12 pf (5% tolerance) load capacitors. an on-chip pll multiplies the 24 mhz oscillator up to 480 mhz, as required by the transceiver/phy, and the internal counters divide it down for use as the 8051 clock. the default 8051 clock frequency is 12 mhz. the clock frequency of the 8051 is dynamically changed by the 8051 through the cpucs register. the clkout pin, which is three-stated and inverted using the internal control bits, outputs the 50% duty cycle 8051 clock at the selected 8051 clock frequency which is 48, 24, or 12 mhz. usarts fx1 contains two standard 8051 usarts, addressed by special function register (sfr) bits. the usart interface pins are available on separate i/o pins, and are not multiplexed with port pins. uart0 and uart1 can operate using an internal clock at 230 kbaud with no more than 1% baud rate error. 230 kbaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. the internal clock adjusts for the 8051 clock rate (48, 24, 12 mhz) such that it always presents the correct frequency for 230-kbaud operation. [1] special function registers certain 8051 sfr addresses are populated to provide fast access to critical fx1 functions. these sfr additions are shown in table 1 on page 5 . bold type indicates non-standard, enhanced 8051 registers. the two sfr rows that end with ?0? and ?8? contain bit addressable registers. the four i/o ports a?d use the sfr addresses used in the standard 8051 for ports 0?3, which are not implemented in the fx1. because of the faster and more efficient sfr addressing, the fx1 i/o ports are not addressable in the external ram space (using the movx instruction). note 1. 115-kbaud operation is also possible by programming the 8051 smod0 or smod1 bits to a ?1? for uart0 and uart1, respectively.
cy7c64713 document number: 38-08039 rev. *l page 5 of 74 figure 1. crystal configuration i 2 c bus fx1 supports the i 2 c bus as a master only at 100/400 khz. scl and sda pins have open drain outputs and hysteresis inputs. these signals must be pulled up to 3.3 v, even if no i 2 c device is connected. buses all packages: 8 or 16-bit ?fifo? bidirectional data bus, multiplexed on i/o ports b and d. 128-pin package: adds 16-bit output only 8051 address bus, 8-bit bidirectional data bus. usb boot methods during the power up s equence, internal logic checks the i 2 c port for the connection of an eeprom whose first byte is either 0xc0 or 0xc2. if found, it uses the vid/pid/did values in the eeprom in place of the internally stored values (0xc0). alternatively, it boot-loads the eeprom contents into an internal ram (0xc2). if no eeprom is detected, fx1 enumerates using internally stored descriptors. the default id values for fx1 are vid/pid/did (0x04b4, 0x 6473, 0xaxxx where xxx=chip revision). [2] table 1. special function registers x 8x 9x ax bx cx dx ex fx 0 ioa iob ioc iod scon1 psw acc b 1sp exif int2clr ioe sbuf1 2dpl0 mpage int4clr oea 3dph0 oeb 4 dpl1 oec 5 dph1 oed 6 dps oee 7pcon 8 tcon scon0 ie ip t2con eicon eie eip 9 tmod sbuf0 atl0 autoptrh1 ep2468stat ep01stat rcap2l btl1 autoptrl1 ep24fifoflgs gpiftrig rcap2h cth0 reserved ep68fifoflgs tl2 dth1 autoptrh2 gpifsgldath th2 e ckcon autoptrl2 gpifsgldatlx f reserved autoptrsetup gpifsgldatlnox 12 pf 12 pf 24 mhz 20 pll c1 c2 12-pf capacitor values assumes a trace capacitance of 3 pf per side on a four layer fr4 pca table 2. default id values for fx1 default vid/pid/did vendor id 0x04b4 cypress semiconductor product id 0x6473 ez-usb fx1 device release 0xannn depends on chip revision (nnn = chip revision where first silicon = 001) notes 2. the i 2 c bus scl and sda pins must be pulled up, even if an eeprom is not connected. otherwise this detection method does not work pro perly.
cy7c64713 document number: 38-08039 rev. *l page 6 of 74 renumeration? because the fx1?s configuration is soft, one chip can take on the identities of multiple distinct usb devices. when first plugged into the usb, the fx1 enumerates automatically and downloads firmware and the usb descriptor tables over the usb cable. next, the fx1 enumerates again, this time as a device defined by the downloaded information. this patented two step process, called renumeration, happens instantly when the device is plugged in, with no indication that the initial download step has occurred. two control bits in the usbcs (usb control and status) register control the renumeration proc ess: discon and renum. to simulate a usb disconnect, the firmware sets discon to 1. to reconnect, the firmware clears discon to 0. before reconnecting, the firmware sets or clears the renum bit to indicate if the firmware or the default usb device handles device requests over endpoint zero: renum = 0, the default usb device handles device requests renum = 1, the firmware handles device requests bus-powered applications the fx1 fully supports bus powered designs by enumerating with less than 100 ma as requ ired by the usb specification. interrupt system int2 interrupt request and enable registers fx1 implements an autovector feat ure for int2 and int4. there are 27 int2 (usb) vectors, an d 14 int4 (fifo/gpif) vectors. see ez-usb technical reference manual (trm) for more details. usb-interrupt autovectors the main usb interrupt is shared by 27 interrupt sources. the fx1 provides a second level of interrupt vectoring, called autovectoring, to save code and processing time that is normally required to identify the individual usb interrupt source. when a usb interrupt is asserted, the fx1 pushes the program counter on to its stack and then jumps to address 0x0043, where it expects to find a ?jump? instruction to the usb interrupt service routine. the fx1 jump instruction is encoded as shown in table 3 . if autovectoring is enabled (av2en = 1 in the intsetup register), the fx1 substitutes its int2vec byte. therefore, if the high byte (?page?) of a jump table address is preloaded at location 0x0044, the automatically inserted int2vec byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page. fifo/gpif interrupt (int4) just as the usb interrupt is shared among 27 individual usb-interrupt sources, the fifo/gpif interrupt is shared among 14 individual fifo/gpif source s. the fifo/gpif interrupt, such as the usb interrupt, can employ autovectoring. table 4 on page 7 shows the priority and int4vec values for the 14 fifo/gpif interrupt sources. fifo/gpif interrupt (int4) just as the usb interrupt is shared among 27 individual usb-interrupt sources, the fifo/gpif interrupt is shared among 14 individual fifo/gpif source s. the fifo/gpif interrupt, such as the usb interrupt, can employ autovectoring. table 4 on page 7 shows the priority and int4vec values for the 14 fifo/gpif interrupt sources. table 3. int2 usb interrupts usb interrupt table for int2 priority int2vec value source notes 1 00 sudav setup data available 2 04 sof start of frame 3 08 sutok setup token received 4 0c suspend usb suspend request 5 10 usb reset bus reset 6 14 reserved 7 18 ep0ack fx1 ack?d the control handshake 8 1c reserved 9 20 ep0-in ep0-in ready to be loaded with data 10 24 ep0-out ep0-out has usb data 11 28 ep1-in ep1-in ready to be loaded with data 12 2c ep1-out ep1-out has usb data 13 30 ep2 in: buffer available. out: buffer has data 14 34 ep4 in: buffer available. out: buffer has data 15 38 ep6 in: buffer available. out: buffer has data 16 3c ep8 in: buffer available. out: buffer has data 17 40 ibn in-bulk-nak (any in endpoint)
cy7c64713 document number: 38-08039 rev. *l page 7 of 74 if autovectoring is enabled (av4en = 1 in the intsetup register), the fx1 substitutes its int4vec byte. therefore, if the high byte (?page?) of a jump-table address is preloaded at location 0x0054, the automatica lly inserted int4vec byte at 0x0055 directs the jump to the correct address out of the 14 addresses within the page. when the isr occurs, the fx1 pushes the program counter onto its stack and then jumps to address 0x0053, where it expects to find a ?jump? instruction to the isr interrupt service routine. 18 44 reserved 19 48 ep0ping ep0 out was pinged and it nak?d 20 4c ep1ping ep1 out was pinged and it nak?d 21 50 ep2ping ep2 out was pinged and it nak?d 22 54 ep4ping ep4 out was pinged and it nak?d 23 58 ep6ping ep6 out was pinged and it nak?d 24 5c ep8ping ep8 out was pinged and it nak?d 25 60 errlimit bus errors exceeded the programmed limit 26 64 27 68 reserved 28 6c reserved 29 70 ep2isoerr iso ep2 out pid sequence error 30 74 ep4isoerr iso ep4 out pid sequence error 31 78 ep6isoerr iso ep6 out pid sequence error 32 7c ep8isoerr iso ep8 out pid sequence error table 4. individual fifo/gpif interrupt sources priority int4vec value source notes 1 80 ep2pf endpoint 2 programmable flag 2 84 ep4pf endpoint 4 programmable flag 3 88 ep6pf endpoint 6 programmable flag 4 8c ep8pf endpoint 8 programmable flag 5 90 ep2ef endpoint 2 empty flag [3] 6 94 ep4ef endpoint 4 empty flag 7 98 ep6ef endpoint 6 empty flag 8 9c ep8ef endpoint 8 empty flag 9 a0 ep2ff endpoint 2 full flag 10 a4 ep4ff endpoint 4 full flag 11 a8 ep6ff endpoint 6 full flag 12 ac ep8ff endpoint 8 full flag 13 b0 gpifdone gpif operation complete 14 b4 gpifwf gpif waveform table 3. int2 usb interrupts (continued) usb interrupt table for int2 priority int2vec value source notes note 3. errata: in slave fifo asynchronous word wide mode, if a single word data is transferred from the usb host to ep2, configured as out en dpoint (ep) in the first transaction, then the empty flag behaves incorrectly. this does not happen if the data size is more than one word in the first transaction. for more information, see the ?errata? on page 71.
cy7c64713 document number: 38-08039 rev. *l page 8 of 74 reset and wakeup reset pin the input pin, reset#, resets the fx1 when asserted. this pin has hysteresis and is active lo w. when a crystal is used with the cy7c64713, the reset period mu st allow for the stabilization of the crystal and the pll. this reset period must be approximately 5 ms after vcc has reached 3.0 volts. if the crystal input pin is driven by a clock signal the internal pll stabilizes in 200 ? s after vcc has reached 3.0 v [4] . figure 2 on page 8 shows a power on reset condition and a reset applied during operation. a power on reset is defined as the time a reset is asserted when power is being applied to the circuit. a powered reset is defined to be when the fx1 has been previously powered on and operat ing and the reset# pin is asserted. cypress provides an application note which describes and recommends power on reset implementation and is found on the cypress web site. while the application note discusses the fx2, the information provided applies also to the fx1. for more information on reset implementation for the fx2 family of products visit http://www.cypress.com. figure 2. reset timing plots wakeup pins the 8051 puts itself and the rest of the chip into a power down mode by setting pcon.0 = 1. th is stops the oscillator and pll. when wakeup is asserted by external logic, the oscillator restarts, after the pll stabilizes, and then the 8051 receives a wakeup interrupt. this applies irrespective of whether the fx1 is connected to the usb or not. the fx1 exits the power down (usb suspend) state using one of the following methods: usb bus activity (if d+/d? lines are left floating, noise on these lines may indicate activity to the fx1 and initiate a wakeup). external logic asserts the wakeup pin. external logic asserts the pa3/wu2 pin. the second wakeup pin, wu2, can also be configured as a general purpose i/o pin. this allows a simple external r-c network to be used as a periodic wakeup source. note that wakeup is by default active low. v il 0 v 3.3 v 3.0 v t reset vcc reset# power on reset t reset vcc reset# v il powered reset 3.3 v 0 v table 5. reset timing values condition t reset power on reset with crystal 5 ms power on reset with external clock 200 ? s + clock stability time powered reset 200 ? s note 4. if the external clock is powered at the same time as the cy 7c64713 and has a stabilization wait period. it must be added to t he 200 ? s.
cy7c64713 document number: 38-08039 rev. *l page 9 of 74 program/data ram size the fx1 has 16 kbytes of inter nal program/data ram, where psen#/rd# signals are internally ored to allow the 8051 to access it as both program and data memory. no usb control registers appear in this space. two memory maps are shown in the following diagrams: figure 3 on page 9 internal code memory, ea = 0 figure 4 on page 10 external code memory, ea = 1. internal code memory, ea = 0 this mode implements the internal 16 kbyte block of ram (starting at 0) as combined code and data memory. when the external ram or rom is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. this allows the user to connect a 64 kbyte memory without requiring the address decodes to keep clear of internal memory spaces. only the internal 16 kbytes and scratch pad 0.5 kbytes ram spaces have the following access: usb download usb upload setup data pointer i 2 c interface boot load figure 3. internal code memory, ea = 0. inside fx1 outside fx1 7.5 kbytes usb regs and 4k fifo buffers (rd#,wr#) 0.5 kbytes ram data (rd#,wr#)* (ok to populate data memory here?rd#/wr# strobes are not active) 40 kbytes external data memory (rd#,wr#) (ok to populate data memory here?rd#/wr# strobes are not active) 16 kbytes ram code and data (psen#,rd#,wr#)* 48 kbytes external code memory (psen#) (ok to populate program memory here? psen# strobe is not active) ffff e200 e1ff e000 3fff 0000 data code *sudptr, usb upload/download, i 2 c interface boot access
cy7c64713 document number: 38-08039 rev. *l page 10 of 74 external code memory, ea = 1 the bottom 16 kbytes of program memory is external, and therefore the bott om 16 kbytes of internal ram is accessible only as da ta memory. figure 4. external code memory, ea = 1 inside fx1 outside fx1 7.5 kbytes usb regs and 4k fifo buffers (rd#,wr#) 0.5 kbytes ram data (rd#,wr#)* (ok to populate data memory here?rd#/wr# strobes are not active) 40 kbytes external data memory (rd#,wr#) (ok to populate data memory here?rd#/wr# strobes are not active) 16 kbytes ram data (rd#,wr#)* 64 kbytes external code memory (psen#) ffff e200 e1ff e000 3fff 0000 data code *sudptr, usb upload/download, i 2 c interface boot access
cy7c64713 document number: 38-08039 rev. *l page 11 of 74 figure 5. register addresses endpoint ram size 3 64 bytes (endpoints 0 and 1) 8 512 bytes (endpoints 2, 4, 6, 8) organization ep0?bidirectional endpoint zero, 64 byte buffer ep1in, ep1out?64 byte buffers, bulk or interrupt ep2, 4, 6, 8?eight 512-byte buffers, bulk, interrupt, or isochronous, of which only the transfer size is available. ep4 and ep8 are double buffered, while ep2 and 6 are either double, triple, or quad buffered. regardless of the physical size of the buffer, each endpoint bu ffer accommodates only one full speed packet. for bulk endpoints, the maximum number of bytes it can accommodate is 64, even though the physical buffer size is 512 or 1024. for an isochronous endpoint the maximum number of bytes it can accommodate is 1023. for endpoint configuration options, see figure 6 on page 12 . setup data buffer a separate 8-byte buffer at 0xe6b8-0xe6bf holds the setup data from a control transfer. default alternate settings in the following table, ?0? means ?not implemented?, and ?2? means ?double buffered?. external fifo interface architecture the fx1 slave fifo architecture has eight 512-byte blocks in the endpoint ram that directly se rve as fifo memories, and are controlled by fifo control signals (such as ifclk, slcs#, slrd, slwr, sloe, pktend, and flags). the usable size of these buffers depend on the usb transfer mode as described in the section organization . in operation, some of the eight ra m blocks fill or empty from the sie, while the others are connected to the i/o transfer logic. the transfer logic takes two forms: the gpif for internally generated control signals or the slave fifo interface for externally controlled transfers. ffff e800 e7bf e740 e73f e700 e6ff e500 e4ff e480 e47f e400 e200 e1ff e000 e3ff efff 2 kbytes reserved 64 bytes ep0 in/out 64 bytes reserved 8051 addressable registers reserved (128) 128 bytes gpif waveforms 512 bytes 8051 xdata ram f000 (512) reserved (512) e780 64 bytes ep1out e77f 64 bytes ep1in e7ff e7c0 4 kbytes ep2-ep8 buffers (8 x 512) not all space is available for all transfer types table 6. default alternate settings alternate setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2) 64 int out (2) 64 iso out (2) ep4 0 64 bulk out (2) 64 bulk out (2) 64 bulk out (2) ep6 0 64 bulk in (2) 64 int in (2) 64 iso in (2) ep8 0 64 bulk in (2) 64 bulk in (2) 64 bulk in (2)
cy7c64713 document number: 38-08039 rev. *l page 12 of 74 figure 6. endpoint configuration master/slave control signals the fx1 endpoint fifos are implemented as eight physically distinct 256 16 ram blocks. the 8051/sie can switch any of the ram blocks between two domains: the usb (sie) domain and the 8051-i/o unit domain. this switching is done instantaneously, giving essentially zero transfer time between ?usb fifos? and ?slave fifos?. while they are physically the same memory, no bytes are actually transferred between buffers. at any time, some ram blocks fill or empty with usb data under sie control, while ot her ram blocks are available to the 8051 and the i/o control unit. the ram blocks operate as a single-port in the usb domain, and dual port in the 8051-i/o domain. the blocks are configured as single, double, triple, or quad buffered. the i/o control unit implements either an internal master (m for master) or external master (s for slave) interface. in master (m) mode, the gpif inte rnally controls fifoadr[1..0] to select a fifo. the rdy pins (two in the 56-pin package, six in the 100-pin and 128-pin packages) are used as flag inputs from an external fifo or other lo gic if desired. the gpif is run from either an internally deriv ed clock or an externally supplied clock (ifclk), at a rate that transfers data up to 96 megabytes/s (48 mhz ifclk with 16-bit interface). in slave (s) mode, the fx1 accepts either an internally derived clock or an externally supplie d clock (ifclk with a maximum frequency of 48 mhz) and slcs#, slrd, slwr, sloe, pktend signals from external logic. when using an external ifclk, the external clock must be present before switching to the external clock with the ifclksrc bit. each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a slave fifo output enable signal sloe enables data of the selected widt h. external logic must ensure that the output enable si gnal is inactive when writing data to a slave fifo. the slave interface can also operate asynchronously, where the slrd and slwr signals act directly as strobes, rather than a clock qualifier as in the synchronous mode. the signals slrd, slwr, sloe, and pktend are gated by the signal slcs#. gpif and fifo clock rates an 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 mhz and 48 mhz. alternatively, an externally supplied clock of 5 to 48 mhz feeding the ifclk pin is used as the interface clock. ifclk is configured to function as an output clock when the gpif and fifos are internally clocked. an output enable bit in the ifconfig register turns this clock output off, if desired. another bit within the ifconfig register inverts the ifclk signal whether internally or externally sourced. gpif the gpif is a flexible 8 or 16-b it parallel interface driven by a user programmable finite state machine. it allows the cy7c64713 to perform local bus mastering, and can implement a wide variety of protocols such as ata interface, printer parallel port, and utopia. the gpif has six programmable control outputs (ctl), nine address outputs (gpifadrx), and six general purpose ready inputs (rdy). the data bus width is 8 or 16 bits. each gpif vector defines the state of th e control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. the gpif vector is programmed to advance a fifo to the next data value, advance an address, and so on. a sequence of the gpif vectors create a single waveform that executes to perform the data move between the fx1 and the external device. six control out signals the 100-pin and 128-pin packages bring out all six control output pins (ctl0?ctl5). the 8051 programs the gpif unit to define the ctl waveforms. the 56-pin package brings out three 64 64 64 64 64 1023 1023 1023 1023 1023 1023 1023 64 64 64 64 64 64 64 64 64 64 ep2 ep2 ep2 ep6 ep6 ep8 ep8 ep0 in&out ep1 in ep1 out 1023 1023 ep6 1023 64 64 ep8 64 64 ep6 64 64 64 64 ep2 64 64 ep4 64 64 ep2 64 64 ep4 64 64 ep2 64 64 ep4 64 64 ep2 64 64 64 64 ep2 64 64 64 64 ep2 64 64 1023 ep2 1023 1023 ep2 1023 1023 ep2 1023 64 64 ep6 1023 1023 ep6 64 64 ep8 64 64 ep6 64 64 64 64 ep6 1023 1023 ep6 64 64 ep8 64 64 ep6 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 1 2 3 4 5 6 7 8 9 10 11 12
cy7c64713 document number: 38-08039 rev. *l page 13 of 74 of these signals: ctl0?ctl2. ctlx waveform edges are programmed to make transitions as fast as once per clock (20.8 ns using a 48 mhz clock). six ready in signals the 100-pin and 128-pin packages bring out all six ready inputs (rdy0?rdy5). the 8051 programs the gpif unit to test the rdy pins for gpif branching. the 56 pin package brings out two of these signals, rdy0?1. nine gpif address out signals nine gpif address lines are available in the 100-pin and 128-pin packages: gpifadr[8..0]. the gpif address lines allow indexing through up to a 512 byte block of ram. if more address lines are needed, i/o port pins are used. long transfer mode in master mode, the 8051 appropriately sets the gpif transaction count registers (gpiftcb3, gpiftcb2, gpiftcb1, or gpiftcb0) for unattended transfers of up to 2 32 transactions. the gpif automatically throttles data flow to prevent under or overflow until the full number of requested transactions are complete. the gpif decrements the value in these registers to represent the current status of the transaction. ecc generation the ez-usb fx1 can calculate eccs (error correcting codes) on data that pass across its gpif or slave fifo interfaces. there are two ecc configurations: two eccs, each calculated over 256 bytes (smartmedia? standard); and one ecc calculated over 512 bytes. the ecc can correct any one-bit error or detect any two-bit error. note to use the ecc logic, the gp if or slave fifo interface must be configured for byte-wide operation. ecc implementation the two ecc configurations ar e selected by the eccm bit: 0.0.0.1 eccm = 0 two 3-byte eccs, each calculated over a 256-byte block of data. this configuration conforms to the smartmedia standard. write any value to eccreset, then pass data across the gpif or slave fifo interface. the e cc for the first 256 bytes of data is calculated and stored in ecc1. the ecc for the next 256 bytes is stored in ecc2. after the se cond ecc is calculated, the values in the eccx registers do not change until the eccreset is written again, even if more data is subsequently passed across the interface. 0.0.0.2 eccm = 1 one 3-byte ecc calculated over a 512-byte block of data. write any value to eccreset, then pass data across the gpif or slave fifo interface. the ecc for the first 512 bytes of data is calculated and stored in ecc1; ecc2 is not used. after the ecc is calculated, the value in ecc1 does not change until the eccreset is written again, even if more data is subsequently passed across the interface usb uploads and downloads the core has the ability to directly edit the data contents of the internal 16 kbyte ram and of the internal 512 byte scratch pad ram via a vendor specific comma nd. this capability is normally used when ?soft? downloading user code and is available only to and from the internal ram, only when the 8051 is held in reset. the available ram spaces are 16 kbytes from 0x0000?0x3fff (code/data) and 512 bytes from 0xe000?0xe1ff (scratch pad data ram). [5] autopointer access fx1 provides two identical autopointers. they are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. this capability is available to and from both internal and external ram. the autopointers are avail able in external fx1 registers, under the control of a mode bit (autoptrsetup.0). using the external fx1 autopointer access (at 0xe67b?0xe67c) allows the autopointer to access all ram, internal and external, to the part. also, the autopointers can point to any fx1 register or endpoint buffer space. when autopointer access to external memory is enabled, the location 0xe67b and 0xe67c in xdata and the code space cannot be used. i 2 c controller fx1 has one i 2 c port that is driven by two internal controllers: one that automatically operates at boot time to load vid/pid/did and configuration information; a nd another that the 8051, once running, uses to control external i 2 c devices. the i 2 c port operates in master mode only. i 2 c port pins the i 2 c pins scl and sda must have external 2.2 k ? pull up resistors even if no eeprom is connected to the fx1. external eeprom device address pins must be configured properly. see ta b l e 7 for configuring the device address pins. table 7. strap boot eeprom address lines to these values bytes example eeprom a2 a1 a0 16 24lc00 [6] n/a n/a n/a 128 24lc01 0 0 0 256 24lc02 0 0 0 4k 24lc32 0 0 1 8k 24lc64 0 0 1 16k 24lc128 0 0 1 notes 5. after the data is downloaded from the host, a ?loader? executes from the internal ram to transfer downloaded data to the exte rnal memory. 6. this eeprom has no address pins.
cy7c64713 document number: 38-08039 rev. *l page 14 of 74 i 2 c interface boot load access at power on reset the i 2 c interface boot loader loads the vid/pid/did configuration by tes and up to 16 kbytes of program/data. the available ram spaces are 16 kbytes from 0x0000?0x3fff and 512 bytes from 0xe000?0xe1ff. the 8051 is in reset. i 2 c interface boot loads only occur after power on reset. i 2 c interface general purpose access the 8051 can control peripherals connected to the i 2 c bus using the i2ctl and i2dat registers. fx1 provides i 2 c master control only, because it is never an i 2 c slave. compatible with previous generation ez-usb fx2 the ez-usb fx1 is fit, form, and function upgradable to the ez-usb fx2lp. this makes for an easy transition for designers wanting to upgr ade their systems from fu ll speed to high speed designs. the pinout and package selection are identical, and all firmware developed for the fx1 function in the fx2lp with proper addition of high speed descriptors and speed switching code. pin assignments figure 7 on page 15 identifies all signals for the three package types. the following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128, 100, and 56-pin packages. the signals on the left edge of the 56-pin package in figure 7 on page 15 are common to all versions in the fx1 family. three modes are available in all package versions: port, gpif master, and slave fifo. these modes define the signals on the right edge of the diagram. the 8051 selects the interface mode using the ifconfig[1:0] register bits . port mode is the power on default configuration. the 100-pin package adds functionality to the 56-pin package by adding these pins: portc or alternate gpifadr[7:0] address signals porte or alternate gpifadr[8] address signal and seven additional 8051 signals three gpif control signals four gpif ready signals nine 8051 signals (two usarts, three timer inputs, int4,and int5#) bkpt, rd#, wr#. the 128-pin package adds the 8051 address and data buses plus control signals. note that two of the required signals, rd# and wr#, are present in the 100- pin version. in the 100-pin and 128-pin versions, an 8051 control bit is set to pulse the rd# and wr# pins when the 8051 reads fr om and writes to the portc.
cy7c64713 document number: 38-08039 rev. *l page 15 of 74 figure 7. signals rdy0 rdy1 ctl0 ctl1 ctl2 int0#/pa0 int1#/pa1 pa2 wu2/pa3 pa4 pa5 pa6 pa7 56 bkpt portc7/gpifadr7 portc6/gpifadr6 portc5/gpifadr5 portc4/gpifadr4 portc3/gpifadr3 portc2/gpifadr2 portc1/gpifadr1 portc0/gpifadr0 pe7/gpifadr8 pe6/t2ex pe5/int6 pe4/rxd1out pe3/rxd0out pe2/t2out pe1/t1out pe0/t0out rxd0 txd0 rxd1 txd1 int4 int5# t2 t1 t0 100 d7 d6 d5 d4 d3 d2 d1 d0 ea 128 rd# wr# cs# oe# psen# a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 xtalin xtalout reset# wakeup# scl sda ifclk clkout dplus dminus fd[15] fd[14] fd[13] fd[12] fd[11] fd[10] fd[9] fd[8] fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] slrd slwr flaga flagb flagc int0#/ pa0 int1#/ pa1 sloe wu2/pa3 fifoadr0 fifoadr1 pktend pa7/flagd/slcs# fd[15] fd[14] fd[13] fd[12] fd[11] fd[10] fd[9] fd[8] fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 int0#/pa0 int1#/pa1 pa2 wu2/pa3 pa4 pa5 pa6 pa7 port gpif master slave fifo ctl3 ctl4 ctl5 rdy2 rdy3 rdy4 rdy5
cy7c64713 document number: 38-08039 rev. *l page 16 of 74 figure 8. cy7c64713 128-pin tqfp pin assignment clkout vcc gnd rdy0/*slrd rdy1/*slwr rdy2 rdy3 rdy4 rdy5 avcc xtalout xtalin agnd nc nc nc avcc dplus dminus agnd a11 a12 a13 a14 a15 vcc gnd int4 t0 t1 t2 *ifclk reserved bkpt ea scl sda oe# pd0/fd8 *wakeup vcc reset# ctl5 a3 a2 a1 a0 gnd pa7/*flagd/slcs# pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 d7 d6 d5 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc gnd pc7/gpifadr7 pc6/gpifadr6 pc5/gpifadr5 pc4/gpifadr4 pc3/gpifadr3 pc2/gpifadr2 pc1/gpifadr1 pc0/gpifadr0 ctl2/*flagc ctl1/*flagb ctl0/*flaga vcc ctl4 ctl3 gnd pd1/fd9 pd2/fd10 pd3/fd11 int5# vcc pe0/t0out pe1/t1out pe2/t2out pe3/rxd0out pe4/rxd1out pe5/int6 pe6/t2ex pe7/gpifadr8 gnd a4 a5 a6 a7 pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 gnd a8 a9 a10 cy7c64713 128-pin tqfp 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 vcc d4 d3 d2 d1 d0 gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 rxd1 txd1 rxd0 txd0 gnd vcc pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 vcc cs# wr# rd# psen# * indicates programmable polarity
cy7c64713 document number: 38-08039 rev. *l page 17 of 74 figure 9. cy7c64713 100-pin tqfp pin assignment pd0/fd8 *wakeup vcc reset# ctl5 gnd pa7/*flagd/slcs# pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc gnd pc7/gpifadr7 pc6/gpifadr6 pc5/gpifadr5 pc4/gpifadr4 pc3/gpifadr3 pc2/gpifadr2 pc1/gpifadr1 pc0/gpifadr0 ctl2/*flagc ctl1/*flagb ctl0/*flaga vcc ctl4 ctl3 pd1/fd9 pd2/fd10 pd3/fd11 int5# vcc pe0/t0out pe1/t1out pe2/t2out pe3/rxd0out pe4/rxd1out pe5/int6 pe6/t2ex pe7/gpifadr8 gnd pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 gnd clkout cy7c64713 100-pin tqfp gnd vcc gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 rxd1 txd1 rxd0 txd0 gnd vcc pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 vcc wr# rd# 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 vcc gnd rdy0/*slrd rdy1/*slwr rdy2 rdy3 rdy4 rdy5 avcc xtalout xtalin agnd nc nc nc avcc dplus dminus agnd vcc gnd int4 t0 t1 t2 *ifclk reserved bkpt scl sda 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 * indicates programmable polarity
cy7c64713 document number: 38-08039 rev. *l page 18 of 74 figure 10. cy7c64713 56-pin ssop pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pd5/fd13 pd6/fd14 pd7/fd15 gnd clkout vcc gnd rdy0/*slrd rdy1/*slwr avcc xtalout xtalin agnd avcc dplus dminus agnd vcc gnd *ifclk reserved scl sda vcc pb0/fd0 pb1/fd1 pb2/fd2 pb3/fd3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pd4/fd12 pd3/fd11 pd2/fd10 pd1/fd9 pd0/fd8 *wakeup vcc reset# gnd pa7/*flagd/slcs# pa6/pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc ctl2/*flagc ctl1/*flagb ctl0/*flaga gnd vcc gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 cy7c64713 56-pin ssop * indicates programmable polarity
cy7c64713 document number: 38-08039 rev. *l page 19 of 74 figure 11. cy7c64713 56-pin qfn pin assignment 28 27 26 25 24 23 22 21 20 19 18 17 16 15 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 reset# gnd pa7/*flagd/slcs# pa6/*pktend pa5/fifoadr1 pa4/fifoadr0 pa3/*wu2 pa2/*sloe pa1/int1# pa0/int0# vcc ctl2/*flagc ctl1/*flagb ctl0/*flaga rdy0/*slrd rdy1/*slwr avcc xtalout xtalin agnd avcc dplus dminus agnd vcc gnd *ifclk reserved vcc *wakeup pd0/fd8 pd1/fd9 pd2/fd10 pd3/fd11 pd4/fd12 pd5/fd13 pd6/fd14 pd7/fd15 gnd clkout vcc gnd gnd vcc gnd pb7/fd7 pb6/fd6 pb5/fd5 pb4/fd4 pb3/fd3 pb2/fd2 pb1/fd1 pb0/fd0 vcc sda scl cy7c64713 56-pin qfn * indicates programmable polarity
cy7c64713 document number: 38-08039 rev. *l page 20 of 74 cy7c64713 pin definitions the fx1 pin definitions for cy7c64713 follow. [7] table 8. fx1 pin definitions 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description 109103avccpowern/a analog vcc . connect this pin to 3.3 v power source. this signal provides power to the analog section of the chip. 17 16 14 7 avcc power n/a analog vcc . connect this pin to 3.3 v power source. this signal provides power to the analog section of the chip. 13 12 13 6 agnd ground n/a analog ground . connect to ground with as short a path as possible. 20 19 17 10 agnd ground n/a analog ground . connect to ground with as short a path as possible. 19 18 16 9 dminus i/o/z z usb d? signal . connect to the usb d? signal. 18 17 15 8 dplus i/o/z z usb d+ signal . connect to the usb d+ signal. 94 a0 output l 8051 address bus . this bus is driven at all times. when the 8051 is addressing the internal ram it reflects the internal address. 95 a1 output l 96 a2 output l 97 a3 output l 117 a4 output l 118 a5 output l 119 a6 output l 120 a7 output l 126 a8 output l 127 a9 output l 128 a10 output l 21 a11 output l 22 a12 output l 23 a13 output l 24 a14 output l 25 a15 output l 59 d0 i/o/z z 8051 data bus . this bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. the data bus is used for external 8051 program and data memory. the data bus is active only for external bus accesses, and is driven low in suspend. 60 d1 i/o/z z 61 d2 i/o/z z 62 d3 i/o/z z 63 d4 i/o/z z 86 d5 i/o/z z 87 d6 i/o/z z 88 d7 i/o/z z 39 psen# output h program store enable . this active low signal indicates an 8051 code fetch from external memory. it is active for program memory fetches from 0x4000?0xffff when the ea pin is low, or from 0x0000?0xffff when the ea pin is high. note 7. do not leave unused inputs floating. tie either high or low as appropriate. pull outputs up or down to ensure signals at powe r up and in standby. note that no pins must be driven when the device is powered down.
cy7c64713 document number: 38-08039 rev. *l page 21 of 74 34 28 bkpt output l breakpoint . this pin goes active (high) when the 8051 address bus matches the bpaddrh/l registers and breakpoints are enabled in t he breakpt register (bpen = 1). if the bppulse bit in the bre akpt register is high, this signal pulses high for eight 12-/24-/48 mhz clocks. if the bppulse bit is low, the signal remains high until the 8051 clears the break bit (by writin g ?1? to it) in the breakpt register. 99 77 49 42 reset# input n/a active low reset . resets the entire chip. see the section reset and wakeup on page 8 for more details. 35 ea input n/a external access . this pin determines where the 8051 fetches code between addresses 0x0000 and 0x3fff. if ea = 0 the 8051 fetches this code from its internal ram. if ea = 1 the 8051 fetches this code fr om external memory. 12 11 12 5 xtalin input n/a crystal input . connect this signal to a 24 mhz parallel-resonant, fundamental mode crystal and load capacitor to gnd. it is also correct to drive the xtalin with an external 24 mhz square wave derived from another clock source. when driving from an external source, the driving signal must be a 3.3 v square wave. 11 10 11 4 xtalout output n/a crystal output . connect this signal to a 24 mhz parallel-resonant, fundamental mode crystal and load capacitor to gnd. if an external clock is used to drive xtalin, leave this pin open. 1 100 5 54 clkout o/z 12 mhz clkout . 12, 24 or 48 mhz clock, phase locked to the 24 mhz input clock. the 8051 defaults to 12 mhz operation. the 8051 may three-state this output by setting cpucs.1 = 1. port a 82 67 40 33 pa0 or int0# i/o/z i (pa0) multiplexed pin whose func tion is selected by portacfg.0 pa0 is a bidirectional i/o port pin. int0# is the active-low 8051 int0 interrupt input signal, which is either edge triggered (it0 = 1) or level triggered (it0 = 0). 83 68 41 34 pa1 or int1# i/o/z i (pa1) multiplexed pin whos e function is selected by: portacfg.1 pa1 is a bidirectional i/o port pin. int1# is the active-low 8051 int1 interrupt input signal, which is either edge triggered (it1 = 1) or level triggered (it1 = 0). 84 69 42 35 pa2 or sloe i/o/z i (pa2) multiplexed pin whose function is selected by two bits: ifconfig[1:0]. pa2 is a bidirectional i/o port pin. sloe is an input-only output enable with programmable polarity (fifopinpolar.4) for the slave fifos connected to fd[7..0] or fd[15..0]. 85 70 43 36 pa3 or wu2 i/o/z i (pa3) multiplexed pin whos e function is selected by: wakeup.7 and oea.3 pa3 is a bidirectional i/o port pin. wu2 is an alternate source for usb wakeup, enabled by wu2en bit (wakeup.1) and polarity set by wu2pol (wakeup.4). if the 8051 is in suspend and wu2en = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the su spend mode. asserting this pin inhibits the chip from suspending, if wu2en = 1. table 8. fx1 pin definitions (continued) 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description
cy7c64713 document number: 38-08039 rev. *l page 22 of 74 89 71 44 37 pa4 or fifoadr0 i/o/z i (pa4) multiplexed pin whos e function is selected by: ifconfig[1..0]. pa4 is a bidirectional i/o port pin. fifoadr0 is an input-only address select for the slave fifos connected to fd[7..0] or fd[15..0]. 90 72 45 38 pa5 or fifoadr1 i/o/z i (pa5) multiplexed pin whos e function is selected by: ifconfig[1..0]. pa5 is a bidirectional i/o port pin. fifoadr1 is an input-only address select for the slave fifos connected to fd[7..0] or fd[15..0]. 91 73 46 39 pa6 or pktend i/o/z i (pa6) multiplexed pin whos e function is selected by the ifconfig[1:0] bits. pa6 is a bidirectional i/o port pin. pktend is an input used to commit the fifo packet data to the endpoint and whose polarity is programmable via fifopinpolar.5. 92 74 47 40 pa7 or flagd or slcs# i/o/z i (pa7) multiplexed pin whos e function is selected by the ifconfig[1:0] and portacfg.7 bits. pa7 is a bidirectional i/o port pin. flagd is a programmable slave-fifo output status flag signal. slcs# gates all other slave fifo enable/strobes port b 44 34 25 18 pb0 or fd[0] i/o/z i (pb0) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb0 is a bidirectional i/o port pin. fd[0] is the bidirectional fifo/gpif data bus. 45 35 26 19 pb1 or fd[1] i/o/z i (pb1) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb1 is a bidirectional i/o port pin. fd[1] is the bidirectional fifo/gpif data bus. 46 36 27 20 pb2 or fd[2] i/o/z i (pb2) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb2 is a bidirectional i/o port pin. fd[2] is the bidirectional fifo/gpif data bus. 47 37 28 21 pb3 or fd[3] i/o/z i (pb3) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb3 is a bidirectional i/o port pin. fd[3] is the bidirectional fifo/gpif data bus. 54 44 29 22 pb4 or fd[4] i/o/z i (pb4) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb4 is a bidirectional i/o port pin. fd[4] is the bidirectional fifo/gpif data bus. 55 45 30 23 pb5 or fd[5] i/o/z i (pb5) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb5 is a bidirectional i/o port pin. fd[5] is the bidirectional fifo/gpif data bus. 56 46 31 24 pb6 or fd[6] i/o/z i (pb6) multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. pb6 is a bidirectional i/o port pin. fd[6] is the bidirectional fifo/gpif data bus. table 8. fx1 pin definitions (continued) 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description
cy7c64713 document number: 38-08039 rev. *l page 23 of 74 57 47 32 25 pb7 or fd[7] i/o/z i (pb7) multiplexed pin whose functi on is selected by the following bits: ifconfig[1..0]. pb7 is a bidirectional i/o port pin. fd[7] is the bidirectional fifo/gpif data bus. port c 72 57 pc0 or gpifadr0 i/o/z i (pc0) multiplexed pin whose f unction is selected by portccfg.0 pc0 is a bidirectional i/o port pin. gpifadr0 is a gpif address output pin. 73 58 pc1 or gpifadr1 i/o/z i (pc1) multiplexed pin whose f unction is selected by portccfg.1 pc1 is a bidirectional i/o port pin. gpifadr1 is a gpif address output pin. 74 59 pc2 or gpifadr2 i/o/z i (pc2) multiplexed pin whose f unction is selected by portccfg.2 pc2 is a bidirectional i/o port pin. gpifadr2 is a gpif address output pin. 75 60 pc3 or gpifadr3 i/o/z i (pc3) multiplexed pin whose f unction is selected by portccfg.3 pc3 is a bidirectional i/o port pin. gpifadr3 is a gpif address output pin. 76 61 pc4 or gpifadr4 i/o/z i (pc4) multiplexed pin whose f unction is selected by portccfg.4 pc4 is a bidirectional i/o port pin. gpifadr4 is a gpif address output pin. 77 62 pc5 or gpifadr5 i/o/z i (pc5) multiplexed pin whose f unction is selected by portccfg.5 pc5 is a bidirectional i/o port pin. gpifadr5 is a gpif address output pin. 78 63 pc6 or gpifadr6 i/o/z i (pc6) multiplexed pin whose f unction is selected by portccfg.6 pc6 is a bidirectional i/o port pin. gpifadr6 is a gpif address output pin. 79 64 pc7 or gpifadr7 i/o/z i (pc7) multiplexed pin whose f unction is selected by portccfg.7 pc7 is a bidirectional i/o port pin. gpifadr7 is a gpif address output pin. port d 102 80 52 45 pd0 or fd[8] i/o/z i (pd0) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[8] is the bidirectional fifo/gpif data bus. 103 81 53 46 pd1 or fd[9] i/o/z i (pd1) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[9] is the bidirectional fifo/gpif data bus. 104 82 54 47 pd2 or fd[10] i/o/z i (pd2) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[10] is the bidirectional fifo/gpif data bus. 105 83 55 48 pd3 or fd[11] i/o/z i (pd3) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[11] is the bidirectional fifo/gpif data bus. 121 95 56 49 pd4 or fd[12] i/o/z i (pd4) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[12] is the bidirectional fifo/gpif data bus. 122 96 1 50 pd5 or fd[13] i/o/z i (pd5) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[13] is the bidirectional fifo/gpif data bus. 123 97 2 51 pd6 or fd[14] i/o/z i (pd6) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[14] is the bidirectional fifo/gpif data bus. table 8. fx1 pin definitions (continued) 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description
cy7c64713 document number: 38-08039 rev. *l page 24 of 74 124 98 3 52 pd7 or fd[15] i/o/z i (pd7) multiplexed pin whos e function is selected by the ifconfig[1..0] and epxfifocfg.0 (wordwide) bits. fd[15] is the bidirectional fifo/gpif data bus. port e 108 86 pe0 or t0out i/o/z i (pe0) multiplexed pin whose func tion is selected by the portecfg.0 bit. pe0 is a bidirectional i/o port pin. t0out is an active high signal from 8051 timer-counter0. t0out outputs a high level fo r one clkout clock cycle when timer0 overflows. if timer0 is operated in mode 3 (two separate timer/counters), t0out is active when the low byte timer/counter overflows. 109 87 pe1 or t1out i/o/z i (pe1) multiplexed pin whose func tion is selected by the portecfg.1 bit. pe1 is a bidirectional i/o port pin. t1out is an active high signal from 8051 timer-counter1. t1out outputs a high level fo r one clkout clock cycle when timer1 overflows. if timer1 is operated in mode 3 (two separate timer/counters), t1out is active when the low byte timer/counter overflows. 110 88 pe2 or t2out i/o/z i (pe2) multiplexed pin whose func tion is selected by the portecfg.2 bit. pe2 is a bidirectional i/o port pin. t2out is the active high output signal from 8051 timer2. t2out is active (high) for one clock cycle when timer/counter 2 overflows. 111 89 pe3 or rxd0out i/o/z i (pe3) multiplexed pin whose func tion is selected by the portecfg.3 bit. pe3 is a bidirectional i/o port pin. rxd0out is an active high signal from 8051 uart0. if rxd0out is selected and uart0 is in mode 0, this pin provides the output data for ua rt0 only when it is in sync mode. otherwise it is a 1. 112 90 pe4 or rxd1out i/o/z i (pe4) multiplexed pin whose func tion is selected by the portecfg.4 bit. pe4 is a bidirectional i/o port pin. rxd1out is an active high output from 8051 uart1. when the rxd1out is selected and uart1 is in mode 0, this pin provides the output data for ua rt1 only when it is in sync mode. in modes 1, 2, and 3, this pin is high. 113 91 pe5 or int6 i/o/z i (pe5) multiplexed pin whose func tion is selected by the portecfg.5 bit. pe5 is a bidirectional i/o port pin. int6 is the 8051 int6 interrupt request input signal. the int6 pin is edge-sensitive, active high. 114 92 pe6 or t2ex i/o/z i (pe6) multiplexed pin whose func tion is selected by the portecfg.6 bit. pe6 is a bidirectional i/o port pin. t2ex is an active high input signal to the 8051 timer2. t2ex reloads timer 2 on its falling edge. t2ex is active only if the exen2 bit is set in t2con. 115 93 pe7 or gpifadr8 i/o/z i (pe7) multiplexed pin whose func tion is selected by the portecfg.7 bit. pe7 is a bidirectional i/o port pin. gpifadr8 is a gpif address output pin. table 8. fx1 pin definitions (continued) 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description
cy7c64713 document number: 38-08039 rev. *l page 25 of 74 4381rdy0 or slrd input n/a multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. rdy0 is a gpif input signal. slrd is the input-only read strobe with programmable polarity (fifopinpolar.3) for the slav e fifos connected to fd[7..0] or fd[15..0]. 5492rdy1 or slwr input n/a multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. rdy1 is a gpif input signal. slwr is the input-only write strobe with programmable polarity (fifopinpolar.2) for the slav e fifos connected to fd[7..0] or fd[15..0]. 6 5 rdy2 input n/a rdy2 is a gpif input signal. 7 6 rdy3 input n/a rdy3 is a gpif input signal. 8 7 rdy4 input n/a rdy4 is a gpif input signal. 9 8 rdy5 input n/a rdy5 is a gpif input signal. 69 54 36 29 ctl0 or flaga o/z h multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. ctl0 is a gpif control output. flaga is a programmable slave-fifo output status flag signal. defaults to programmable for the fifo selected by the fifoadr[1:0] pins. 70 55 37 30 ctl1 or flagb o/z h multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. ctl1 is a gpif control output. flagb is a programmable slave-fifo output status flag signal. defaults to full for the fifo selected by the fifoadr[1:0] pins. 71 56 38 31 ctl2 or flagc o/z h multiplexed pin whose function is selected by the following bits: ifconfig[1..0]. ctl2 is a gpif control output. flagc is a programmable slave-fifo output status flag signal. defaults to empty for the fifo selected by the fifoadr[1:0] pins. 66 51 ctl3 o/z h ctl3 is a gpif control output. 67 52 ctl4 output h ctl4 is a gpif control output. 98 76 ctl5 output h ctl5 is a gpif control output. 32 26 20 13 ifclk i/o/z z interface clock, used for synchronously clocking data into or out of the slave fifos. ifclk also serves as a timing reference for all slave fifo control si gnals and gpif. when internal clocking is used (ifconfig.7 = 1) the ifclk pin is configured to output 30/48 mhz by bits ifconfig.5 and ifconfig.6. ifclk may be inverted, whether internally or externally sourced, by setting the bit ifconfig.4 = 1. 28 22 int4 input n/a int4 is the 8051 int4 interrupt request input signal. the int4 pin is edge-sensitive, active high. 106 84 int5# input n/a int5# is the 8051 int5 interrupt request input signal. the int5 pin is edge-sensitive, active low. table 8. fx1 pin definitions (continued) 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description
cy7c64713 document number: 38-08039 rev. *l page 26 of 74 31 25 t2 input n/a t2 is the active-high t2 input signal to 8051 timer2, which provides the input to timer2 when c/t2 = 1. when c/t2 = 0, timer2 does not use this pin. 30 24 t1 input n/a t1 is the active-high t1 signal for 8051 timer1, which provides the input to timer1 when c/t1 is 1. when c/t1 is 0, timer1 does not use this bit. 29 23 t0 input n/a t0 is the active-high t0 signal for 8051 timer0, which provides the input to timer0 when c/t0 is 1. when c/t0 is 0, timer0 does not use this bit. 53 43 rxd1 input n/a rxd1 is an active-high input signal for 8051 uart1, which provides data to the uart in all modes. 52 42 txd1 output h txd1 is an active-high output pin from 8051 uart1, which provides the output clock in syn c mode, and the output data in async mode. 51 41 rxd0 input n/a rxd0 is the active-high rxd0 input to 8051 uart0, which provides data to the uart in all modes. 50 40 txd0 output h txd0 is the active-high txd0 output from 8051 uart0, which provides the output clock in syn c mode, and the output data in async mode. 42 cs# output h cs# is the active-low chip select for external memory. 41 32 wr# output h wr# is the active-low write stro be output for external memory. 40 31 rd# output h rd# is the active-low read strobe output for external memory. 38 oe# output h oe# is the active low output enable for external memory. 33 27 21 14 reserved input n/a reserved . connect to ground. 101 79 51 44 wakeup input n/a usb wakeup . if the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. holding wakeup asserted inhibits the ez-usb fx1 chip from suspending. this pin has programmable polarity (wakeup.4). 36 29 22 15 scl od z clock for the i 2 c interface . connect to vcc with a 2.2k resistor, even if no i 2 c peripheral is attached. 37 30 23 16 sda od z data for i 2 c interface . connect to vcc with a 2.2k resistor, even if no i 2 c peripheral is attached. 2 1 6 55 vcc power n/a vcc . connect to 3.3 v power source. 26 20 18 11 vcc power n/a vcc . connect to 3.3 v power source. 43 33 24 17 vcc power n/a vcc . connect to 3.3 v power source. 48 38 vcc power n/a vcc . connect to 3.3 v power source. 64 49 34 27 vcc power n/a vcc . connect to 3.3 v power source. 68 53 vcc power n/a vcc . connect to 3.3 v power source. 81 66 39 32 vcc power n/a vcc . connect to 3.3 v power source. 100 78 50 43 vcc power n/a vcc . connect to 3.3 v power source. 107 85 vcc power n/a vcc . connect to 3.3 v power source. 3 2 7 56 gnd ground n/a ground . 27 21 19 12 gnd ground n/a ground . table 8. fx1 pin definitions (continued) 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description
cy7c64713 document number: 38-08039 rev. *l page 27 of 74 49 39 gnd ground n/a ground . 58 48 33 26 gnd ground n/a ground . 65 50 35 28 gnd ground n/a ground . 80 65 gnd ground n/a ground . 93 75 48 41 gnd ground n/a ground . 116 94 gnd ground n/a ground . 125 99 4 53 gnd ground n/a ground . 14 13 nc n/a n/a no connect . this pin must be left open. 15 14 nc n/a n/a no connect . this pin must be left open. 16 15 nc n/a n/a no connect . this pin must be left open. table 8. fx1 pin definitions (continued) 128-pin tqfp 100-pin tqfp 56-pin ssop 56-pin qfn name type default description
document number: 38-08039 rev. *l page 28 of 74 cy7c64713 register summary fx1 register bit definitions are described in the ez-usb trm in greater detail. table 9. fx1 register summary hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access gpif waveform memories e400 128 wavedata gpif waveform descriptor 0, 1, 2, 3 data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e480 128 reserved general configuration e600 1 cpucs cpu control & status 0 0 portcstb clkspd1 clkspd0 clkinv clkoe 8051res 00000010 rrbbbbbr e601 1 ifconfig interface configuration (ports, gpif, slave fifos) ifclksrc 3048mhz ifclkoe ifclkpol async gstate ifcfg1 ifcfg0 10000000 rw e602 1 pinflagsab [8] slave fifo flaga and flagb pin configuration flagb3 flagb2 flagb1 flagb0 flaga3 flaga2 flaga1 flaga0 00000000 rw e603 1 pinflagscd [8] slave fifo flagc and flagd pin configuration flagd3 flagd2 flagd1 flagd0 flagc3 flagc2 flagc1 flagc0 00000000 rw e604 1 fiforeset [8] restore fifos to default state nakall 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e605 1 breakpt breakpoint control 0 0 0 0 break bppulse bpen 0 00000000 rrrrbbbr e606 1 bpaddrh breakpoint address h a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e607 1 bpaddrl breakpoint address l a7 a6 a5 a4 a3 a2 a1 a0 xxxxxxxx rw e608 1 uart230 230 kbaud internally generated ref. clock 0 0 0 0 0 0 230uart1 230uart0 00000000 rrrrrrbb e609 1 fifopinpolar [8] slave fifo interface pins polarity 0 0 pktend sloe slrd slwr ef ff 00000000 rrbbbbbb e60a 1 revid chip revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 reva 00000001 r e60b 1 revctl [8] chip revision control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb note 8. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 29 of 74 cy7c64713 udma e60c 1 gpifholdamount mstb hold time (for udma) 0 0 0 0 0 0 holdtime1 holdtime0 00000000 rrrrrrbb 3 reserved endpoint configuration e610 1 ep1outcfg endpoint 1-out configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e611 1 ep1incfg endpoint 1-in configuration valid 0 type1 type0 0 0 0 0 10100000 brbbrrrr e612 1 ep2cfg endpoint 2 configuration valid dir type1 type0 size 0 buf1 buf0 10100010 bbbbbrbb e613 1 ep4cfg endpoint 4 configuration valid dir type1 type0 0 0 0 0 10100000 bbbbrrrr e614 1 ep6cfg endpoint 6 configuration valid dir type1 type0 size 0 buf1 buf0 11100010 bbbbbrbb e615 1 ep8cfg endpoint 8 configuration valid dir type1 type0 0 0 0 0 11100000 bbbbrrrr 2 reserved e618 1 ep2fifocfg [9] endpoint 2 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e619 1 ep4fifocfg [9] endpoint 4 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61a 1 ep6fifocfg [9] endpoint 6 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61b 1 ep8fifocfg [9] endpoint 8 / slave fifo configuration 0 infm1 oep1 autoout autoin zerolenin 0 wordwide 00000101 rbbbbbrb e61c 4 reserved e620 1 ep2autoinlenh [9] endpoint 2 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e621 1 ep2autoinlenl [9] endpoint 2 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 9. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 30 of 74 cy7c64713 e622 1 ep4autoinlenh [10] endpoint 4 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e623 1 ep4autoinlenl [10] endpoint 4 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e624 1 ep6autoinlenh [10] endpoint 6 autoin packet length h 0 0 0 0 0 pl10 pl9 pl8 00000010 rrrrrbbb e625 1 ep6autoinlenl [10] endpoint 6 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e626 1 ep8autoinlenh [10] endpoint 8 autoin packet length h 0 0 0 0 0 0 pl9 pl8 00000010 rrrrrrbb e627 1 ep8autoinlenl [10] endpoint 8 autoin packet length l pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 00000000 rw e628 1 ecccfg ecc configu- ration 0 0 0 0 0 0 0 eccm 00000000 rrrrrrrb e629 1 eccreset ecc reset x x x x x x x x 00000000 w e62a 1 ecc1b0 ecc1 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 11111111 r e62b 1 ecc1b1 ecc1 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 11111111 r e62c 1 ecc1b2 ecc1 byte 2 address col5 col4 col3 col2 col1 col0 line17 line16 11111111 r e62d 1 ecc2b0 ecc2 byte 0 address line15 line14 line13 line12 line11 line10 line9 line8 11111111 r e62e 1 ecc2b1 ecc2 byte 1 address line7 line6 line5 line4 line3 line2 line1 line0 11111111 r e62f 1 ecc2b2 ecc2 byte 2 address col5 col4 col3 col2 col1 col0 0 0 11111111 r table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 10. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 31 of 74 cy7c64713 e630 1 ep2fifopfh [11] endpoint 2 / slave fifo programmable flag h iso mode decis pktstat in: pkts[2] out:pfc12 in: pkts[1] out:pfc11 in: pkts[0] out:pfc10 0 pfc9 pfc8 10001000 bbbbbrbb e630 1 ep2fifopfh [11] endpoint 2 / slave fifo programmable flag h non-iso mode decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 10001000 bbbbbrbb e631 1 ep2fifopfl [11] endpoint 2 / slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e632 1 ep4fifopfh [11] endpoint 4 / slave fifo programmable flag h iso mode decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 10001000 bbrbbrrb e632 1 ep4fifopfh [11] endpoint 4 / slave fifo programmable flag h non-iso mode decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 10001000 bbrbbrrb e633 1 ep4fifopfl [11] endpoint 4 / slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e634 1 ep6fifopfh [11] endpoint 6 / slave fifo programmable flag h iso mode decis pktstat inpkts[2] out:pfc12 in: pkts[1] out:pfc11 in: pkts[0] out:pfc10 0 pfc9 pfc8 00001000 bbbbbrbb e634 1 ep6fifopfh [11] endpoint 6 / slave fifo programmable flag h non-iso mode decis pktstat out:pfc12 out:pfc11 out:pfc10 0 pfc9 in:pkts[2] out:pfc8 00001000 bbbbbrbb table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 11. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 32 of 74 cy7c64713 e635 1 ep6fifopfl [12] endpoint 6 / slave fifo programmable flag l in:pkts[1] out:pfc7 in:pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e636 1 ep8fifopfh [12] endpoint 8 / slave fifo programmable flag h iso mode decis pktstat 0 in: pkts[1] out:pfc10 in: pkts[0] out:pfc9 0 0 pfc8 00001000 bbrbbrrb e636 1 ep8fifopfh [12] endpoint 8 / slave fifo programmable flag h non-iso mode decis pktstat 0 out:pfc10 out:pfc9 0 0 pfc8 00001000 bbrbbrrb e637 1 ep8fifopfl [12] iso mode endpoint 8 / slave fifo programmable flag l pfc7 pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw e637 1 ep8fifopfl [12] non-iso mode endpoint 8 / slave fifo programmable flag l in: pkts[1] out:pfc7 in: pkts[0] out:pfc6 pfc5 pfc4 pfc3 pfc2 pfc1 pfc0 00000000 rw 8 reserved e640 1 reserved e641 1 reserved e642 1 reserved e643 1 reserved e644 4 reserved e648 1 inpktend [12] force in packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w e649 7 outpktend [12] force out packet end skip 0 0 0 ep3 ep2 ep1 ep0 xxxxxxxx w interrupts e650 1 ep2fifoie [14] endpoint 2 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 12. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 33 of 74 cy7c64713 e651 1 ep2fifoirq [13, 14] endpoint 2 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000111 rrrrrbbb e652 1 ep4fifoie [14] endpoint 4 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e653 1 ep4fifoirq [13, 14] endpoint 4 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000111 rrrrrbbb e654 1 ep6fifoie [14] endpoint 6 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e655 1 ep6fifoirq [15, 16] endpoint 6 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000110 rrrrrbbb e656 1 ep8fifoie [16] endpoint 8 slave fifo flag interrupt enable 0 0 0 0 edgepf pf ef ff 00000000 rw e657 1 ep8fifoirq [13, 14] endpoint 8 slave fifo flag interrupt request 0 0 0 0 0 pf ef ff 00000110 rrrrrbbb e658 1 ibnie in-bulk-na k interrupt enable 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00000000 rw e659 1 ibnirq [13] in-bulk-na k interrupt request 0 0 ep8 ep6 ep4 ep2 ep1 ep0 00xxxxxx rrbbbbbb e65a 1 nakie endpoint ping-nak / ibn interrupt enable ep8 ep6 ep4 ep2 ep1 ep0 0 ibn 00000000 rw e65b 1 nakirq [13] endpoint ping-nak / ibn interrupt request ep8 ep6 ep4 ep2 ep1 ep0 0 ibn xxxxxx0x bbbbbbrb table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access notes 13. sfrs not part of the standard 8051 architecture. 14. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 34 of 74 cy7c64713 e65c 1 usbie usb int enables 0 ep0ack 0 ures susp sutok sof sudav 00000000 rw e65d 1 usbirq [15] usb interrupt requests 0 ep0ack 0 ures susp sutok sof sudav 0xxxxxxx rbbbbbbb e65e 1 epie endpoint interrupt enables ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 00000000 rw e65f 1 epirq [15] endpoint interrupt requests ep8 ep6 ep4 ep2 ep1out ep1in ep0out ep0in 0 rw e660 1 gpifie [16] gpif interrupt enable 0 0 0 0 0 0 gpifwf gpifdone 00000000 rw e661 1 gpifirq [16] gpif interrupt request 0 0 0 0 0 0 gpifwf gpifdone 000000xx rw e662 1 usberrie usb error interrupt enables isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 00000000 rw e663 1 usberrirq [15] usb error interrupt requests isoep8 isoep6 isoep4 isoep2 0 0 0 errlimit 0000000x bbbbrrrb e664 1 errcntlim usb error counter and limit ec3 ec2 ec1 ec0 limit3 limit2 limit1 limit0 xxxx0100 rrrrbbbb e665 1 clrerrcnt clear error counter ec3:0 x x x x x x x x xxxxxxxx w e666 1 int2ivec interrupt 2 (usb) autovector 0 i2v4 i2v3 i2v2 i2v1 i2v0 0 0 00000000 r e667 1 int4ivec interrupt 4 (slave fifo & gpif) autovector 1 0 i4v3 i4v2 i4v1 i4v0 0 0 10000000 r e668 1 intsetup interrupt 2 & 4 setup 0 0 0 0 av2en 0 int4src av4en 00000000 rw e669 7 reserved input / output e670 1 portacfg i/o porta alternate configuration flagd slcs 0 0 0 0 int1 int0 00000000 rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access notes 15. sfrs not part of the standard 8051 architecture. 16. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 35 of 74 cy7c64713 e671 1 portccfg i/o portc alternate configuration gpifa7 gpifa6 gpifa5 gpifa4 gpifa3 gpifa2 gpifa1 gpifa0 00000000 rw e672 1 portecfg i/o porte alternate configuration gpifa8 t2ex int6 rxd1out rxd0out t2out t1out t0out 00000000 rw e673 4 xtalinsrc xtalin clock source 0 0 0 0 0 0 0 extclk 00000000 rrrrrrrb e677 1 reserved e678 1 i2cs i2c bus control & status start stop lastrd id1 id0 berr ack done 000xx000 bbbrrrrr e679 1 i2dat i2c bus data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67a 1 i2ctl i2c bus control 0 0 0 0 0 0 stopie 400khz 00000000 rw e67b 1 xautodat1 autoptr1 movx access, when aptren = 1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e67c 1 xautodat2 autoptr2 movx access, when aptren = 1 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw udma crc e67d 1 udmacrch [17] udma crc msb crc15 crc14 crc13 crc12 crc11 crc10 crc9 crc8 01001010 rw e67e 1 udmacrcl [17] udma crc lsb crc7 crc6 crc5 crc4 crc3 crc2 crc1 crc0 10111010 rw e67f 1 udmacrc-qualifier udma crc qualifier qenable 0 0 0 qstate qsignal2 qsignal1 qsignal0 00000000 brrrbbbb usb control e680 1 usbcs usb control & status 0 0 0 0 discon nosynsof renum sigrsume x0000000 rrrrbbbb e681 1 suspend put chip into suspend x x x x x x x x xxxxxxxx w e682 1 wakeupcs wakeup control & status wu2 wu wu2pol wupol 0 dpen wu2en wuen xx000101 bbbbrbbb e683 1 togctl toggle control q s r i/o ep3 ep2 ep1 ep0 x0000000 rrrbbbbb e684 1 usbframeh usb frame count h 0 0 0 0 0 fc10 fc9 fc8 00000xxx r table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 17. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 36 of 74 cy7c64713 e685 1 usbframel usb frame count l fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 xxxxxxxx r e686 1 reserved e687 1 fnaddr usb function address 0 fa6 fa5 fa4 fa3 fa2 fa1 fa0 0xxxxxxx r e688 2 reserved endpoints e68a 1 ep0bch [18] endpoint 0 byte count h (bc15) (bc14) (bc13) (bc12) (bc11) (bc10) (bc9) (bc8) xxxxxxxx rw e68b 1 ep0bcl [18] endpoint 0 byte count l (bc7) bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e68c 1 reserved e68d 1 ep1outbc endpoint 1 out byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e68e 1 reserved e68f 1 ep1inbc endpoint 1 in byte count 0 bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e690 1 ep2bch [18] endpoint 2 byte count h 0 0 0 0 0 bc10 bc9 bc8 xxxxxxxx rw e691 1 ep2bcl [18] endpoint 2 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e692 2 reserved e694 1 ep4bch [18] endpoint 4 byte count h 0 0 0 0 0 0 bc9 bc8 xxxxxxxx rw e695 1 ep4bcl [18] endpoint 4 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e696 2 reserved e698 1 ep6bch [18] endpoint 6 byte count h 0 0 0 0 0 bc10 bc9 bc8 xxxxxxxx rw e699 1 ep6bcl [18] endpoint 6 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e69a 2 reserved e69c 1 ep8bch [18] endpoint 8 byte count h 0 0 0 0 0 0 bc9 bc8 xxxxxxxx rw e69d 1 ep8bcl [18] endpoint 8 byte count l bc7/skip bc6 bc5 bc4 bc3 bc2 bc1 bc0 xxxxxxxx rw e69e 2 reserved table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 18. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 37 of 74 cy7c64713 e6a0 1 ep0cs endpoint 0 control and status hsnak 0 0 0 0 0 busy stall 10000000 bbbbbbrb e6a1 1 ep1outcs endpoint 1 out control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb e6a2 1 ep1incs endpoint 1 in control and status 0 0 0 0 0 0 busy stall 00000000 bbbbbbrb e6a3 1 ep2cs endpoint 2 control and status 0 npak2 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb e6a4 1 ep4cs endpoint 4 control and status 0 0 npak1 npak0 full empty 0 stall 00101000 rrrrrrrb e6a5 1 ep6cs endpoint 6 control and status 0 npak2 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a6 1 ep8cs endpoint 8 control and status 0 0 npak1 npak0 full empty 0 stall 00000100 rrrrrrrb e6a7 1 ep2fifoflgs endpoint 2 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a8 1 ep4fifoflgs endpoint 4 slave fifo flags 0 0 0 0 0 pf ef ff 00000010 r e6a9 1 ep6fifoflgs endpoint 6 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6aa 1 ep8fifoflgs endpoint 8 slave fifo flags 0 0 0 0 0 pf ef ff 00000110 r e6ab 1 ep2fifobch endpoint 2 slave fifo total byte count h 0 0 0 bc12 bc11 bc10 bc9 bc8 00000000 r e6ac 1 ep2fifobcl endpoint 2 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6ad 1 ep4fifobch endpoint 4 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access
document number: 38-08039 rev. *l page 38 of 74 cy7c64713 e6ae 1 ep4fifobcl endpoint 4 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6af 1 ep6fifobch endpoint 6 slave fifo total byte count h 0 0 0 0 bc11 bc10 bc9 bc8 00000000 r e6b0 1 ep6fifobcl endpoint 6 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b1 1 ep8fifobch endpoint 8 slave fifo total byte count h 0 0 0 0 0 bc10 bc9 bc8 00000000 r e6b2 1 ep8fifobcl endpoint 8 slave fifo total byte count l bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 00000000 r e6b3 1 sudptrh setup data pointer high address byte a15 a14 a13 a12 a11 a10 a9 a8 xxxxxxxx rw e6b4 1 sudptrl setup data pointer low address byte a7 a6 a5 a4 a3 a2 a1 0 xxxxxxx0 bbbbbbbr e6b5 1 sudptrctl setup data pointer auto mode 0 0 0 0 0 0 0 sdpauto 00000001 rw 2 reserved e6b8 8 setupdat 8 bytes of setup data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r setupdat[0] = bmrequestty pe setupdat[1] = bmrequest setupdat[2: 3] = wvalue setupdat[4: 5] = windex setupdat[6: 7] = wlength gpif e6c0 1 gpifwfselect waveform selector singlewr1 singlewr0 singlerd1 singlerd0 fifowr1 fifowr0 fiford1 fiford0 11100100 rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access
document number: 38-08039 rev. *l page 39 of 74 cy7c64713 e6c1 1 gpifidlecs gpif done, gpif idle drive mode done 0 0 0 0 0 0 idledrv 10000000 rw e6c2 1 gpifidlectl inactive bus, ctl states 0 0 ctl5 ctl4 ctl3 ctl2 ctl1 ctl0 11111111 rw e6c3 1 gpifctlcfg ctl drive type trictl 0 ctl5 ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6c4 1 gpifadrh [19] gpif address h 0 0 0 0 0 0 0 gpifa8 00000000 rw e6c5 1 gpifadrl [19] gpif address l gpifa7 gpifa6 gpifa5 gpifa4 gpifa3 gpifa2 gpifa1 gpifa0 00000000 rw flowstate e6c6 1 flowstate flowstate enable and selector fse 0 0 0 0 fs2 fs1 fs0 00000000 brrrrbbb e6c7 1 flowlogic flowstate logic lfunc1 lfunc0 terma2 terma1 terma0 termb2 termb1 termb0 00000000 rw e6c8 1 floweq0ctl ctl-pin states in flowstate (when logic = 0) ctl0e3 ctl0e2 ctl0e1/ctl5 ctl0e0/ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6c9 1 floweq1ctl c tl-pin states in flowstate (when logic = 1) ctl0e3 ctl0e2 ctl0e1/ctl5 ctl0e0/ctl4 ctl3 ctl2 ctl1 ctl0 00000000 rw e6ca 1 flowholdoff holdoff configuration hoperiod3 hoperiod2 hoperiod1 hoperiod0 hostate hoctl2 hoctl1 hoctl0 00000000 rw e6cb 1 flowstb flowstate strobe configuration slave rdyasync ctltogl sustain 0 mstb2 mstb1 mstb0 00100000 rw e6cc 1 flowstbedge flowstate rising/falling edge configuration 0 0 0 0 0 0 falling rising 00000001 rrrrrrbb e6cd 1 flowstbperiod master-strobe half-period d7 d6 d5 d4 d3 d2 d1 d0 00000010 rw e6ce 1 gpiftcb3 [19] gpif transaction count byte 3 tc31 tc30 tc29 tc28 tc27 tc26 tc25 tc24 00000000 rw e6cf 1 gpiftcb2 [19] gpif transaction count byte 2 tc23 tc22 tc21 tc20 tc19 tc18 tc17 tc16 00000000 rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 19. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 40 of 74 cy7c64713 e6d0 1 gpiftcb1 [20] gpif transaction count byte 1 tc15 tc14 tc13 tc12 tc11 tc10 tc9 tc8 00000000 rw e6d1 1 gpiftcb0 [20] gpif transaction count byte 0 tc7 tc6 tc5 tc4 tc3 tc2 tc1 tc0 00000001 rw 2 reserved 00000000 rw reserved reserved e6d2 1 ep2gpifflgsel [20] endpoint 2 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6d3 1 ep2gpifpfstop endpoint 2 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo2flag 00000000 rw e6d4 1 ep2gpiftrig [20] endpoint 2 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6da 1 ep4gpifflgsel [20] endpoint 4 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6db 1 ep4gpifpfstop endpoint 4 gpif stop transaction on gpif flag 0 0 0 0 0 0 0 fifo4flag 00000000 rw e6dc 1 ep4gpiftrig [20] endpoint 4 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved reserved reserved e6e2 1 ep6gpifflgsel [20] endpoint 6 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6e3 1 ep6gpifpfstop endpoint 6 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo6flag 00000000 rw e6e4 1 ep6gpiftrig [20] endpoint 6 gpif trigger x x x x x x x x xxxxxxxx w table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 20. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 41 of 74 cy7c64713 3 reserved reserved reserved e6ea 1 ep8gpifflgsel [21] endpoint 8 gpif flag select 0 0 0 0 0 0 fs1 fs0 00000000 rw e6eb 1 ep8gpifpfstop endpoint 8 gpif stop transaction on prog. flag 0 0 0 0 0 0 0 fifo8flag 00000000 rw e6ec 1 ep8gpiftrig [21] endpoint 8 gpif trigger x x x x x x x x xxxxxxxx w 3 reserved e6f0 1 xgpifsgldath gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw e6f1 1 xgpifsgldatlx read/write gpif data l & trigger transaction d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e6f2 1 xgpifsgldatlnox read gpif data l, no transaction trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r e6f3 1 gpifreadycfg internal rdy, sync/async, rdy pin states intrdy sas tcxrdy5 0 0 0 0 0 00000000 bbbrrrrr e6f4 1 gpifreadystat gpif ready status 0 0 rdy5 rdy4 rdy3 rdy2 rdy1 rdy0 00xxxxxx r e6f5 1 gpifabort abort gpif waveforms x x x x x x x x xxxxxxxx w e6f6 2 reserved endpoint buffers e740 64 ep0buf ep0-in/-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e780 64 ep10utbuf ep1-out buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw e7c0 64 ep1inbuf ep1-in buffer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 2048 reserved rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 21. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 42 of 74 cy7c64713 f000 1023 ep2fifobuf 64/1023-byte ep 2 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f400 64 ep4fifobuf 64 byte ep 4 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw f600 64 reserved f800 1023 ep6fifobuf 64/1023-byte ep 6 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fc00 64 ep8fifobuf 64 byte ep 8 / slave fifo buffer (in or out) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw fe00 64 reserved xxxx i2c configuration byte 0 discon 0 0 0 0 0 400khz xxxxxxxx [23] n/a special function registers (sfrs) 80 1 ioa [22] port a (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 81 1 sp stack pointer d7 d6 d5 d4 d3 d2 d1 d0 00000111 rw 82 1 dpl0 data pointer 0 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 83 1 dph0 data pointer 0 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 84 1 dpl1 [22] data pointer 1 l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 85 1 dph1 [22] data pointer 1 h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 86 1 dps [22] data pointer 0/1 select 0 0 0 0 0 0 0 sel 00000000 rw 87 1 pcon power control smod0 x 1 1 x x x idle 00110000 rw 88 1 tcon timer/counter control (bit addressable) tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 rw 89 1 tmod timer/counter mode control gate ct m1 m0 gate ct m1 m0 00000000 rw 8a 1 tl0 timer 0 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access notes 22. sfrs not part of the standard 8051 architecture. 23. if no eeprom is detected by the sie then the default is 00000000.
document number: 38-08039 rev. *l page 43 of 74 cy7c64713 8b 1 tl1 timer 1 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 8c 1 th0 timer 0 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8d 1 th1 timer 1 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw 8e 1 ckcon [24] clock control x x t2m t1m t0m md2 md1 md0 00000001 rw 8f 1 reserved 90 1 iob [24] port b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw 91 1 exif [24] external interrupt flag(s) ie5 ie4 i2cint usbnt 1 0 0 0 00001000 rw 92 1 mpage [24] upper addr byte of movx using @r0 / @r1 a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 93 5 reserved 98 1 scon0 serial port 0 control (bit addressable) sm0_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00000000 rw 99 1 sbuf0 serial port 0 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw 9a 1 autoptrh1 [24] autopointer 1 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9b 1 autoptrl1 [24] autopointer 1 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9c 1 reserved 9d 1 autoptrh2 [24] autopointer 2 address h a15 a14 a13 a12 a11 a10 a9 a8 00000000 rw 9e 1 autoptrl2 [24] autopointer 2 address l a7 a6 a5 a4 a3 a2 a1 a0 00000000 rw 9f 1 reserved a0 1 ioc [24] port c (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw a1 1 int2clr [24] interrupt 2 clear x x x x x x x x xxxxxxxx w a2 1 int4clr [24] interrupt 4 clear x x x x x x x x xxxxxxxx w a3 5 reserved table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 24. sfrs not part of the standard 8051 architecture.
document number: 38-08039 rev. *l page 44 of 74 cy7c64713 a8 1 ie interrupt enable (bit addressable) ea es1 et2 es0 et1 ex1 et0 ex0 00000000 rw a9 1 reserved aa 1 ep2468stat [25] endpoint 2, 4, 6, 8 status flags ep8f ep8e ep6f ep6e ep4f ep4e ep2f ep2e 01011010 r ab 1 ep24fifoflgs [25] endpoint 2, 4 slave fifo status flags 0 ep4pf ep4ef ep4ff 0 ep2pf ep2ef ep2ff 00100010 r ac 1 ep68fifoflgs [25] endpoint 6, 8 slave fifo status flags 0 ep8pf ep8ef ep8ff 0 ep6pf ep6ef ep6ff 01100110 r ad 2 reserved af 1 autoptrsetup [25] autopointer 1&2 setup 0 0 0 0 0 aptr2inc aptr1inc aptren 00000110 rw b0 1 iod [24] port d (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b1 1 ioe [25] port e (not bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw b2 1 oea [25] port a output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b3 1 oeb [25] port b output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b4 1 oec [25] port c output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b5 1 oed [25] port d output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b6 1 oee [25] port e output enable d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw b7 1 reserved b8 1 ip interrupt priority (bit addressable) 1 ps1 pt2 ps0 pt1 px1 pt0 px0 10000000 rw b9 1 reserved ba 1 ep01stat [25] endpoint 0&1 status 0 0 0 0 0 ep1inbsy ep1outbsy ep0bsy 00000000 r bb 1 gpiftrig [25, 26] endpoint 2, 4, 6, 8 gpif slave fifo trigger done 0 0 0 0 rw ep1 ep0 10000xxx brrrrbbb table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access notes 25. sfrs not part of the standard 8051 architecture. 26. read and writes to these register may require synchronization delay, see the section ?synchronization delay? in the ez-usb trm .
document number: 38-08039 rev. *l page 45 of 74 cy7c64713 bc 1 reserved bd 1 gpifsgldath [27] gpif data h (16-bit mode only) d15 d14 d13 d12 d11 d10 d9 d8 xxxxxxxx rw be 1 gpifsgldatlx [27] gpif data l w/ trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx rw bf 1 gpifsgldatlnox [27] gpif data l w/ no trigger d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx r c0 1 scon1 [27] serial port 1 control (bit addressable) sm0_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00000000 rw c1 1 sbuf1 [27] serial port 1 data buffer d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw c2 6 reserved c8 1 t2con timer/counter 2 control (bit addressable) tf2 exf2 rclk tclk exen2 tr2 ct2 cprl2 00000000 rw c9 1 reserved ca 1 rcap2l capture for timer 2, auto-reload, up-counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cb 1 rcap2h capture for timer 2, auto-reload, up-counter d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cc 1 tl2 timer 2 reload l d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw cd 1 th2 timer 2 reload h d15 d14 d13 d12 d11 d10 d9 d8 00000000 rw ce 2 reserved d0 1 psw program status word (bit addressable) cy ac f0 rs1 rs0 ov f1 p 00000000 rw d1 7 reserved d8 1 eicon [27] external interrupt control smod1 1 eresi resi int6 0 0 0 01000000 rw d9 7 reserved e0 1 acc accumulator (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 27. sfrs not part of the standard 8051 architecture.
document number: 38-08039 rev. *l page 46 of 74 cy7c64713 e1 7 reserved e8 1 eie [28] external interrupt enable(s) 1 1 1 ex6 ex5 ex4 ei2c eusb 11100000 rw e9 7 reserved f0 1 b b (bit addressable) d7 d6 d5 d4 d3 d2 d1 d0 00000000 rw f1 7 reserved f8 1 eip [28] external interrupt priority control 1 1 1 px6 px5 px4 pi2c pusb 11100000 rw f9 7 reserved legend (for the access column) r = all bits read-only w = all bits write-only r = read-only bit w = write-only bit b = both read/write bit table 9. fx1 register summary (continued) hex size name description b7 b6 b5 b4 b3 b2 b1 b0 default access note 28. sfrs not part of the standard 8051 architecture.
cy7c64713 document number: 38-08039 rev. *l page 47 of 74 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................. ............... ?65 c to +150 c ambient temperature with power supplied.... 0 c to +70 c supply voltage to ground potentia l..............?0.5 v to +4.0 v dc input voltage to any input pin ......................... 5.25 v [29] dc voltage applied to outputs in high z state ................................... ?0.5 v to vcc + 0.5 v power dissipation...................... .............................. 235 mw static discharge voltage......................................... > 2000 v max output current, per i/o port................................ 10 ma max output current, all five i/o ports (128 and 100 pin packages) ....... .............. .............. .... 50 ma operating conditions t a (ambient temperature under bias) ........... 0 c to +70 c supply voltage..........................................+3.15 v to +3.45 v ground voltage................................................................. 0 v f osc (oscillator or crystal frequency).... 24 mhz 100 ppm parallel resonant usb transceiver usb 2.0 compliant in full speed mode. dc characteristics parameter description conditions min typ max unit vcc supply voltage 3.15 3.3 3.45 v vcc ramp up 0 to 3.3 v 200 ? ? ? s v ih input high voltage 2 ? 5.25 v v il input low voltage ?0.5 ? 0.8 v v ih_x crystal input high voltage 2 ? 5.25 v v il_x crystal input low voltage ?0.05 ? 0.8 v i i input leakage current 0 < v in < vcc ? ? 10 ? a v oh output voltage high i out = 4 ma 2.4 ? ? v v ol output low voltage i out = ?4 ma ? ? 0.4 v i oh output current high ? ? 4 ma i ol output current low ? ? 4 ma c in input pin capacitance except d+/d? ? 3.29 10 pf d+/d? ? 12.96 15 pf i susp suspend current connected ? 0.5 1.2 ma disconnected ? 0.3 1.0 ma i cc supply current 8051 running, connected to usb ? 35 65 ma t reset reset time after valid power vcc min = 3.0 v 5.0 ? ? ms pin reset after powered on 200 ? ? ? s note 29. it is recommended to not power i/o when chip power is off.
cy7c64713 document number: 38-08039 rev. *l page 48 of 74 ac electrical characteristics usb transceiver usb 2.0 compliant in full speed mode. figure 12. program memo ry read timing diagram t cl t dh t soel t scsl psen# d[7..0] oe# a[15..0] cs# t stbl data in t acc1 t av t stbh t av clkout [30] [31] table 10. program memory read parameters parameter description min typ max unit notes t cl 1/clkout frequency ? 20.83 ? ns 48 mhz ? 41.66 ? ns 24 mhz ?83.2? ns12 mhz t av delay from clock to valid address 0 ? 10.7 ns t stbl clock to psen low 0 ? 8 ns t stbh clock to psen high 0 ? 8 ns t soel clock to oe low ? ? 11.1 ns t scsl clock to cs low ? ? 13 ns t dsu data setup to clock 9.6 ? ? ns t dh data hold time 0 ? ? ns notes 30. clkout is shown with positive polarity. 31. t acc1 is computed from the parameters in ta b l e 1 0 as follows: t acc1 (24 mhz) = 3 t cl ? t av ? t dsu = 106 ns t acc1 (48 mhz) = 3 t cl ? t av ? t dsu = 43 ns.
cy7c64713 document number: 38-08039 rev. *l page 49 of 74 figure 13. data memory read timing diagram when using the autpoptr1 or autoptr2 to address external me mory, the address of autoptr1 is active only when either rd# or wr# are active. the address of autoptr2 is active through out the cycle and meets the above address valid time for which is based on the stretch value. data in t cl a[15..0] t av t av rd# t stbl t stbh t dh d[7..0] data in t acc1 [33] t dsu stretch = 0 stretch = 1 t cl a[15..0] t av rd# t dh d[7..0] t acc1 [33] t dsu cs# cs# t scsl oe# t soel clkout [32] clkout [32] table 11. data memory read parameters parameter description min typ max unit notes t cl 1/clkout frequency ? 20.83 ? ns 48 mhz ? 41.66 ? ns 24 mhz ?83.2? ns12 mhz t av delay from clock to valid address ? ? 10.7 ns t stbl clock to rd low ? ? 11 ns t stbh clock to rd high ? ? 11 ns t scsl clock to cs low ? ? 13 ns t soel clock to oe low ? ? 11.1 ns t dsu data setup to clock 9.6 ? ? ns t dh data hold time 0 ? ? ns notes 32. clkout is shown with positive polarity. 33. t acc2 and t acc3 are computed from the parameters in ta b l e 11 as follows: t acc2 (24 mhz) = 3 t cl ? t av ? t dsu = 106 ns t acc2 (48 mhz) = 3 t cl ? t av ? t dsu = 43 ns t acc3 (24 mhz) = 5 t cl ? t av ? t dsu = 190 ns t acc3 (48 mhz) = 5 t cl ? t av ? t dsu = 86 ns.
cy7c64713 document number: 38-08039 rev. *l page 50 of 74 figure 14. data memory write timing diagram when using the autpoptr1 or autoptr2 to address external me mory, the address of autoptr1 is active only when either rd# or wr# are active. the address of autoptr2 is active through out the cycle and meets the above address valid time for which is based on the stretch value. t off1 clkout a[15..0] wr# t av d[7..0] t cl t stbl t stbh data out t off1 clkout a[15..0] wr# t av d[7..0] t cl data out stretch = 1 t on1 t scsl t av cs# t on1 cs# table 12. data memory write parameters parameter description min max unit notes t av delay from clock to valid address 0 10.7 ns t stbl clock to wr pulse low 0 11.2 ns t stbh clock to wr pulse high 0 11.2 ns t scsl clock to cs pulse low ? 13.0 ns t on1 clock to data turn-on 0 13.1 ns t off1 clock to data hold time 0 13.1 ns
cy7c64713 document number: 38-08039 rev. *l page 51 of 74 portc strobe feature timings the rd# and wr# are present in the 100 pin version and the 128 pin package. in these 100 pin and 128 pin versions, an 8051 control bit is set to pulse the rd# and wr# pins when the 8051 reads from or writes to the po rtc. this feature is enabled by setting the portcstb bit in cpucs register. the rd# and wr# strobes are asserted for two clkout cycles when the portc is accessed. the wr# strobe is asserted two clock cycles after the portc is updated and is active for two clock cycles after that as shown in figure 16 . as for read, the value of the portc three clock cycles before the assertion of rd# is the value that the 8051 reads in. the rd# is pulsed for 2 clock cycles afte r 3 clock cycles from the point when the 8051 has performed a read function on portc. in this feature the rd# signal prompts the external logic to prepare the next data byte. nothing gets sampled internally on assertion of the rd# signal itself. it is just a ?prefetch? type signal to get the next data byte prepared. therefore, using it meets the set up time to the next read. the purpose of this pulsing of rd# is to let the external peripheral know that the 8051 is done reading portc and that the data was latched into the portc three clkout cycles prior to asserting the rd# signal. after the rd# is pulsed the external logic may update the data on portc. the timing diagram of the read and write strobing function on accessing portc follows. refer to figure 13 on page 49 and figure 14 on page 50 for details on propagation delay of rd# and wr# signals. figure 16. wr# strobe function when portc is accessed by 8051 figure 17. rd# strobe function when portc is accessed by 8051 clkout wr# t clkout portc is updated t stbl t stbh clkout t clkout data must be held for 3 clk cylces data is updated by external logic 8051 reads portc rd# t stbl t stbh
cy7c64713 document number: 38-08039 rev. *l page 52 of 74 gpif synchronous signals in the following figure, dashed lines indicate signals with programmable polarity. figure 18. gpif synchronous signals timing diagram the following table provides the gpif synchronous signals parameters with internally sourced ifclk. [34, 35] the following table provides the gpif synchronous signals parameters with externally sourced ifclk. [35] data(output) t xgd ifclk rdy x data(input) valid t sry t ryh t ifclk t sgd ctl x t xctl t dah n n+1 gpifadr[8:0] t sga table 13. gpif synchronous signals para meters with internally sourced ifclk parameter description min max unit t ifclk ifclk period 20.83 ? ns t sry rdy x to clock setup time 8.9 ? ns t ryh clock to rdy x 0?ns t sgd gpif data to clock setup time 9.2 ? ns t dah gpif data hold time 0 ? ns t sga clock to gpif address propagation delay ? 7.5 ns t xgd clock to gpif data output propagation delay ? 11 ns t xctl clock to ctl x output propagation delay ? 6.7 ns table 14. gpif synchronous signals para meters with externally sourced ifclk parameter description min max unit t ifclk ifclk period 20.83 200 ns t sry rdy x to clock setup time 2.9 ? ns t ryh clock to rdy x 3.7 ? ns t sgd gpif data to clock setup time 3.2 ? ns t dah gpif data hold time 4.5 ? ns t sga clock to gpif address propagation delay ? 11.5 ns t xgd clock to gpif data output propagation delay ? 15 ns t xctl clock to ctl x output propagation delay ? 10.7 ns notes 34. gpif asynchronous rdy x signals have a minimum setup time of 50 ns when using internal 48-mhz ifclk. 35. ifclk must not exceed 48 mhz.
cy7c64713 document number: 38-08039 rev. *l page 53 of 74 slave fifo synchronous read in the following figure, dashed lines indicate signals with programmable polarity. figure 19. slave fifo synchronous read timing diagram the following table provides the slave fifo synchronou s read parameters with internally sourced ifclk. [36] the following table provides the slave fifo synchr onous read parameters with externally sourced ifclk. [36] ifclk slrd flags sloe t srd t rdh t oeon t xfd t xflg data t ifclk n+1 t oeoff n table 15. slave fifo synchronous read parameters with internally sourced ifclk parameter description min max unit t ifclk ifclk period 20.83 ? ns t srd slrd to clock setup time 18.7 ? ns t rdh clock to slrd hold time 0 ? ns t oeon sloe turn on to fifo data valid ? 10.5 ns t oeoff sloe turn off to fifo data hold ? 10.5 ns t xflg clock to flags output propagation delay ? 9.5 ns t xfd clock to fifo data output propagation delay ? 11 ns table 16. slave fifo synchronous read parameters with externally sourced ifclk parameter description min max unit t ifclk ifclk period 20.83 200 ns t srd slrd to clock setup time 12.7 ? ns t rdh clock to slrd hold time 3.7 ? ns t oeon sloe turn on to fifo data valid ? 10.5 ns t oeoff sloe turn off to fifo data hold ? 10.5 ns t xflg clock to flags output propagation delay ? 13.5 ns t xfd clock to fifo data output propagation delay ? 15 ns note 36. ifclk must not exceed 48 mhz.
cy7c64713 document number: 38-08039 rev. *l page 54 of 74 slave fifo asynchronous read in the following figure, dashed lines indicate signals with programmable polarity. figure 20. slave fifo asynchronous read timing diagram in the following table, the slave fifo asynchronous parameter values use internal ifclk setting at 48 mhz . table 17. slave fifo asynchronous read parameters parameter description min max unit t rdpwl slrd pulse width low 50 ? ns t rdpwh slrd pulse width high 50 ? ns t xflg slrd to flags output propagation delay ? 70 ns t xfd slrd to fifo data output propagation delay ? 15 ns t oeon sloe turn-on to fifo data valid ? 10.5 ns t oeoff sloe turn-off to fifo data hold ? 10.5 ns slrd flags t rdpwl t rdpwh sloe t xflg t xfd data t oeon t oeoff n+1 n
cy7c64713 document number: 38-08039 rev. *l page 55 of 74 slave fifo synchronous write in the following figure, dashed lines indicate signals with programmable polarity. figure 21. slave fifo synchronous write timing diagram the following table provides the slave fifo synchronou s write parameters with internally sourced ifclk. [37] the following table provides the slave fifo synchronou s write parameters with externally sourced ifclk. [37] table 18. slave fifo synchronous write parameters with internally sourced ifclk parameter description min max unit t ifclk ifclk period 20.83 ? ns t swr slwr to clock setup time 18.1 ? ns t wrh clock to slwr hold time 0 ? ns t sfd fifo data to clock setup time 9.2 ? ns t fdh clock to fifo data hold time 0 ? ns t xflg clock to flags output propagation time ? 9.5 ns table 19. slave fifo synchronous write parameters with externally sourced ifclk [37] parameter description min max unit t ifclk ifclk period 20.83 200 ns t swr slwr to clock setup time 12.1 ? ns t wrh clock to slwr hold time 3.6 ? ns t sfd fifo data to clock setup time 3.2 ? ns t fdh clock to fifo data hold time 4.5 ? ns t xflg clock to flags output propagation time ? 13.5 ns z z t sfd t fdh data ifclk slwr flags t wrh t xflg t ifclk t swr n note 37. ifclk must not exceed 48 mhz.
cy7c64713 document number: 38-08039 rev. *l page 56 of 74 slave fifo asynchronous write in the following figure, dashed lines indicate signals with programmable polarity. figure 22. slave fifo asynchronous write timing diagram in the following table, the slave fifo asynchronous parameter values use internal ifclk setting at 48 mhz. slave fifo synchronous packet end strobe in the following figure, dashed lines indicate signals with programmable polarity. figure 23. slave fifo synchronou s packet end strobe timing diagram the following table provides the slave fifo synchronous pa cket end strobe parameters with internally sourced ifclk. [38] data t sfd t fdh flags t xfd slwr/slcs# t wrpwh t wrpwl table 20. slave fifo asynchronous write parameters with internally sourced ifclk parameter description min max unit t wrpwl slwr pulse low 50 ? ns t wrpwh slwr pulse high 70 ? ns t sfd slwr to fifo data setup time 10 ? ns t fdh fifo data to slwr hold time 10 ? ns t xfd slwr to flags output propagation delay ? 70 ns table 21. slave fifo synchronous packet end stro be parameters with in ternally sourced ifclk parameter description min max unit t ifclk ifclk period 20.83 ? ns t spe pktend to clock setup time 14.6 ? ns t peh clock to pktend hold time 0 ? ns t xflg clock to flags output propagation delay ? 9.5 ns flags t xflg ifclk pktend t spe t peh note 38. ifclk must not exceed 48 mhz.
cy7c64713 document number: 38-08039 rev. *l page 57 of 74 the following table provides the slave fifo synchronous packe t end strobe parameters with externally sourced ifclk. [39] there is no specific timing requirement that needs to be met for asserting the pktend pin concerning asserting slwr. pktend is asserted with the last data value clocked into the fifos or thereafter. the only cons ideration is that the set up time t spe and the hold time t peh for pktend must be met. although there are no specific ti ming requirements for asserting pktend in relation to slwr, there exists a specific case condition that needs attention. when using the pktend to commit a one byte or word packet, an additional timing requirement must be met when the fifo is configured to operate in auto mode and it is necessary to send two packets back to back: a full packet (defined as the number of bytes in the fifo meeting the level set in the autoinlen register) committed automatically followed by a short one byte or word packet committed manually using the pktend pin. in this particular scenario, the developer must assert the pktend at least one clock cycle after the rising edge that caused the last byte or word to be clocked into the previous auto committed packet. figure 24 shows this scenario. x is the value the autoinlen register is set to when the in endpoint is configured to be in auto mode. figure 24 shows a scenario where two packets are being committed. the first packet is committed automatically when the number of bytes in the fifo reaches x (value set in autoinlen register) and the second one byte or word short packet being committed manually using pktend. note that there is at least one ifclk cycle timing between asserting pktend and clocking of the last byte of the previous packet (causing the packet to be committed automatically). failing to adhere to this timing results in the fx2 failing to send the one byte or word short packet. figure 24. slave fifo synchronou s write sequence and timing diagram table 22. slave fifo synchronous packet end strobe parameters with externally sourced ifclk parameter description min max unit t ifclk ifclk period 20.83 200 ns t spe pktend to clock setup time 8.6 ? ns t peh clock to pktend hold time 2.5 ? ns t xflg clock to flags output propagation delay ? 13.5 ns ifclk slwr data t ifclk >= t swr >= t wrh x-2 pktend x-3 t fah t spe t peh fifoadr t sfd t sfd t sfd x-4 t fdh t fdh t fdh t sfa 1 x t sfd t sfd t sfd x-1 t fdh t fdh t fdh at least one ifclk cycle note 39. ifclk must not exceed 48 mhz.
cy7c64713 document number: 38-08039 rev. *l page 58 of 74 slave fifo asynchronous packet end strobe in the following figure, dashed lines indicate signals with programmable polarity. figure 25. slave fifo asynchronous packet end strobe timing diagram in the following table, the slave fifo asynchronous parameter values use internal ifclk setting at 48 mhz . slave fifo output enable in the following figure, dashed lines indicate signals with programmable polarity. figure 26. slave fifo output enable timing diagram slave fifo address to flags/data in the following figure, dashed lines indicate signals with programmable polarity. figure 27. slave fifo address to flags/data timing diagram table 23. slave fifo asynchronous packet end strobe parameters parameter description min max unit t pepwl pktend pulse width low 50 ? ns t pwpwh pktend pulse width high 50 ? ns t xflg pktend to flags output propagation delay ? 115 ns flags t xflg pktend t pepwl t pepwh table 24. slave fifo output enable parameters parameter description max unit t oeon sloe assert to fifo data output 10.5 ns t oeoff sloe deassert to fifo data hold 10.5 ns sloe data t oeon t oeoff table 25. slave fifo address to flags/data parameters parameter description max unit t xflg fifoadr[1:0] to flags output propagation delay 10.7 ns t xfd fifoadr[1:0] to fifodata output propagation delay 14.3 ns fifoadr [1.0] data t xflg t xfd flags nn+1
cy7c64713 document number: 38-08039 rev. *l page 59 of 74 slave fifo synchronous address figure 28. slave fifo synchronous address timing diagram the following table provides the slave fifo synchronous address parameters. [40] slave fifo asynchronous address in the following figure, dashed lines indicate signals with programmable polarity. figure 29. slave fifo asynchronous address timing diagram in the following table, the slave fifo asynchronous parameter values use internal ifclk setting at 48 mhz . ifclk slcs/fifoadr [1:0] t sfa t fah table 26. slave fifo synchronous address parameters parameter description min max unit t ifclk interface clock period 20.83 200 ns t sfa fifoadr[1:0] to clock setup time 25 ? ns t fah clock to fifoadr[1:0] hold time 10 ? ns table 27. slave fifo asynchronous address parameters parameter description min unit t sfa fifoadr[1:0] to rd/wr/pktend setup time 10 ns t fah rd/wr/pktend to fifoadr[1:0] hold time 10 ns rd/wr/pktend slcs/fifoadr [1:0] t sfa t fah note 40. ifclk must not exceed 48 mhz.
cy7c64713 document number: 38-08039 rev. *l page 60 of 74 sequence diagram single and burst synchronous read example figure 30. slave fifo synchronous read sequence and timing diagram figure 31. slave fifo synchronous sequence of events diagram figure 30 shows the timing relati onship of the slave fifo signals during a synchronous fifo read using ifclk as the synchronizing clock. this diagram illustrates a single read followed by a burst read. at t = 0 the fifo address is stable and the signal slcs is asserted (slcs may be tied low in some applications). note t sfa has a minimum of 25 ns. this means when ifclk is running at 48 mhz, the fifo address setup time is more than one ifclk cycle. at t = 1, sloe is asserted. sl oe is an output enable only, whose sole function is to drive the data bus. the data that is driven on the bus is the data that the internal fifo pointer is currently pointing to. in this example it is the first data value in the fifo. note the data is pre-fetched and is driven on the bus when sloe is asserted. at t = 2, slrd is asserted. slrd must meet the setup time of t srd (time from asserting the slrd signal to the rising edge of the ifclk) and maintain a minimum hold time of t rdh (time from the ifclk edge to the deassertion of the slrd signal). if the slcs signal is used, it must be asserted with slrd, or before slrd is asserted (that is, the slcs and slrd signals must both be asserted to start a valid read condition). the fifo pointer is updated on the rising edge of the ifclk, while slrd is asserted. this starts the propagation of data from the newly addressed location to the data bus. after a propagation delay of t xfd (measured from the rising edge of ifclk) the new data value is present. n is the first data value read from the fifo. to have data on the fifo data bus, sloe must also be asserted. the same sequence of events are shown for a burst read and are marked with the time indicators of t = 0 through 5. ifclk slrd flags sloe data t srd t rdh t oeon t xfd t xflg t ifclk n+1 data driven: n >= t srd t oeon t xfd n+2 t xfd t xfd >= t rdh t oeoff n+4 n+3 t oeoff t sfa t fah fifoadr slcs t=0 n+1 t=1 t=2 t=3 t=4 t fah t=0 t sfa t=1 t=2 t=3 t=4 nn n+1 n+2 fifo pointer n+3 fifo data bus n+4 not driven driven: n sloe slrd n+1 n+2 n+3 not driven slrd sloe ifclk ifclk ifclk ifclk ifclk n+4 n+4 ifclk ifclk ifclk ifclk slrd n+1 slrd n+1 n+1 sloe not driven n+4 n+4 ifclk sloe
cy7c64713 document number: 38-08039 rev. *l page 61 of 74 note for the burst mode, the slrd and sloe are left asserted during the entire duration of the read. in the burst read mode, when sloe is asserted, data indexed by the fifo pointer is on the data bus. during the first read cycle, on the rising edge of the c lock the fifo pointer is updated and increments to point to address n + 1. for each subsequent rising edge of ifclk, while the slrd is asserted, the fifo pointer is incremented and th e next data value is placed on the data bus. single and burst synchronous write in the following figure, dashed lines indicate signals with programmable polarity. figure 32. slave fifo synchronou s write sequence and timing diagram figure 32 shows the timing relati onship of the slave fifo signals during a synchronous write using ifclk as the synchronizing clock. this diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the pktend pin. at t = 0 the fifo address is stable and the signal slcs is asserted (slcs may be tied low in some applications). note t sfa has a minimum of 25 ns. this means when ifclk is running at 48 mhz, the fifo address setup time is more than one ifclk cycle. at t = 1, the external master or peripheral must output the data value onto the data bus with a minimum set up time of t sfd before the rising edge of ifclk. at t = 2, slwr is asserted. the slwr must meet the setup time of t swr (time from asserting the slwr signal to the rising edge of ifclk) and maintain a minimum hold time of t wrh (time from the ifclk edge to the deassertion of the slwr signal). if slcs signal is used, it mu st be asserted with slwr or before slwr is asserted. (that is the slcs and slwr signals must both be asserted to start a valid write condition). while the slwr is asserted, data is written to the fifo and on the rising edge of the ifclk, the fifo pointer is incremented. the fifo flag is also updated after a delay of t xflg from the rising edge of the clock. the same sequence of events are also shown for a burst write and are marked with the time indicators of t = 0 through 5. note for the burst mode, slwr and slcs are left asserted for the entire duration of writing all the required data values. in this burst write mode, after the slwr is asserted, the data on the fifo data bus is written to th e fifo on every rising edge of ifclk. the fifo pointer is updated on each rising edge of ifclk. in figure 32 , after the four bytes are written to the fifo, slwr is deasserted. the short 4-byte packet is committed to the host by asserting the pktend signal. there is no specific timing r equirement that must be met for asserting the pktend signal with regards to asserting the slwr signal. pktend is asserted with the last data value or thereafter. the only consideration is the setup time t spe and the hold time t peh must be met. in the scenario of figure 32 , the number of data values committed includes the last value written to the fifo. in this example, both the data value and the pktend signal are clocked on the same rising edge of ifclk. pktend is asserted in subsequent clock cycles. the fifoaddr lines must be held constant during the pktend assertion. ifclk slwr flags data t swr t wrh t sfd t xflg t ifclk n >= t swr >= t wrh n+3 pktend n+2 t xflg t sfa t fah t spe t peh fifoadr slcs t sfd t sfd t sfd n+1 t fdh t fdh t fdh t fdh t=0 t=1 t=2 t=3 t sfa t fah t=1 t=0 t=2 t=5 t=3 t=4
cy7c64713 document number: 38-08039 rev. *l page 62 of 74 although there are no specific timing requirement for asserting pktend, there is a specific corner case condition that needs attention while using the pktend to commit a one byte or word packet. additional timing requirements exist when the fifo is configured to operate in auto m ode and it is necessary to send two packets: a full packet (full defined as the number of bytes in the fifo meeting t he level set in autoinlen register) committed automatically followed by a short one byte or word packet committed manually using the pktend pin. in this case, the external master must make sure to assert the pktend pin at least one clock cycle after the rising edge that caused the last byte or word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the autoinlen register). refer to table 19 on page 55 for further details on this timing. sequence diagram of a single and burst asynchronous read figure 33. slave fifo asynchronous read sequence and timing diagram figure 34. slave fifo asynchronous read sequence of events diagram figure 33 shows the timing relati onship of the slave fifo signals during an asynchronous fifo read. it shows a single read followed by a burst read. at t = 0 the fifo address is stable and the slcs signal is asserted. at t = 1, sloe is asserted. this results in the data bus being driven. the data that is driven on to the bus is previous data, it data that was in the fi fo from a prior read cycle. at t = 2, slrd is asserted. the slrd must meet the minimum active pulse of t rdpwl and minimum de-active pulse width of t rdpwh . if slcs is used then, slcs must be in asserted with slrd or before slrd is asserted (that is, the slcs and slrd signals must both be asserted to start a valid read condition). the data that drives after asserting slrd, is the updated data from the fifo. this data is valid after a propagation delay of t xfd from the activating edge of slrd. in figure 33 , data n is the first valid data read from the fifo. for data to appear on the data bus during the read cycle (that is, slrd is asserted), sloe must be in an asserted state. slrd and sloe can also be tied together. the same sequence of events is also shown for a burst read marked with t = 0 through 5. note in burst read mode, during sloe is assertion, the data bus is in a driven state and outputs the previous data. after the slrd is asserted, the data from the fifo is driven on the data bus (sloe must also be asserted) and then the fifo pointer is incremented. slrd flags sloe data t rdpwh t rdpwl t oeon t xfd t xflg n data (x) t xfd n+1 t xfd t oeoff n+3 n+2 t oeoff t xflg t sfa t fah fifoadr slcs driven t xfd t oeon t rdpwh t rdpwl t rdpwh t rdpwl t rdpwh t rdpwl t fah t sfa n t=0 t=0 t=1 t=7 t=2 t=3 t=4 t=5 t=6 t=1 t=2 t=3 t=4 nn sloe slrd fifo pointer n+3 fifo data bus not driven driven: x n not driven sloe n n+2 n+3 slrd n n+1 slrd n+1 slrd n+1 n+2 slrd n+2 slrd n+2 n+1 sloe not driven sloe n n+1 n+1
cy7c64713 document number: 38-08039 rev. *l page 63 of 74 sequence diagram of a single and burst asynchronous write in the following figure, dashed lines indicate signals with programmable polarity. figure 35. slave fifo asynchronous write sequence and timing diagram figure 35 shows the timing relationship of the slave fifo write in an asynchronous mode. this diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using pktend. at t = 0 the fifo address is applied, insuring that it meets the setup time of t sfa . if slcs is used, it must also be asserted (slcs may be tied low in some applications). at t = 1 slwr is asserted. slwr must meet the minimum active pulse of t wrpwl and minimum de-active pulse width of t wrpwh . if the slcs is used, it must be in asserted with slwr or before slwr is asserted. at t = 2, data must be present on the bus t sfd before the deasserting edge of slwr. at t = 3, deasserting slwr causes the data to be written from the data bus to the fifo and then increments the fifo pointer. the fifo flag is also updated after t xflg from the deasserting edge of slwr. the same sequence of events are shown for a burst write and is indicated by the timing marks of t = 0 through 5. note in the burst write mode, afte r slwr is deasserted, the data is written to the fifo and then the fifo pointer is incremented to the next byte in the fifo. the fifo pointer is post incremented. in figure 35 , after the four bytes are written to the fifo and slwr is deasserted, the short 4-byte packet is committed to the host using the pktend. the external device must be designed to not assert slwr and the pktend signal at the same time. it must be designed to assert the pktend after slwr is deasserted and has met the minimum deasserted pulse width. the fifoaddr lines are to be held constant during the pktend assertion. pktend slwr flags data t wrpwh t wrpwl t xflg n t sfd n+1 t xflg t sfa t fah fifoadr slcs t wrpwh t wrpwl t wrpwh t wrpwl t wrpwh t wrpwl t fah t sfa t fdh t sfd n+2 t fdh t sfd n+3 t fdh t sfd t fdh t pepwh t pepwl t=0 t=2 t =1 t=3 t=0 t=2 t=1 t=3 t=6 t=9 t=5 t=8 t=4 t=7
cy7c64713 document number: 38-08039 rev. *l page 64 of 74 ordering information ordering code definitions ordering code package type ram size # prog i/os 8051 address/data busses cy7c64713-128axc 128-pin tqfp - pb-free 16k 40 16/8 bit cy7c64713-100axc 100-pin tqfp - pb-free 16k 40 ? cy7c64713-56pvxc 56-pin ssop - pb-free 16k 24 ? CY7C64713-56LTXC 56-pin qfn - pb-free 16k 24 ? cy3674 ez-usb fx1 development kit tape and reel temperature range: x = c or i or a c = commercial grade; i = industrial grade; a = automotive grade x = pb-free package type: xxxxx = 128a or 100a or 56pv or 56lt 128a = 128-pin tqfp; 100a = 100-pin tqfp; 56pv = 56-pin ssop; 56lt = 56-pin qfn part number family code: 64 = usb technology code: c = cmos marketing code: 7 = cypress products company id: cy = cypress cy 64 - xxxxx x x x 7 c 713
cy7c64713 document number: 38-08039 rev. *l page 65 of 74 package diagrams the fx1 is available in four packages: 56-pin ssop 56-pin qfn 100-pin tqfp 128-pin tqfp figure 36. 56-pin ssop 300 mils o563 51-85062 *f
cy7c64713 document number: 38-08039 rev. *l page 66 of 74 figure 37. 56-pin qfn (8 8 1 mm) lt56b 4.5 5.2 epad (sawn) 001-53450 *d
cy7c64713 document number: 38-08039 rev. *l page 67 of 74 figure 38. 100-pin tqfp (14 20 1.4 mm) a100ra 51-85050 *e
cy7c64713 document number: 38-08039 rev. *l page 68 of 74 figure 39. 128-pin tqfp (14 20 1.4 mm) a128ra quad flat package no leads (qfn) package design notes electrical contact of the part to the printed circuit board (pcb) is made by soldering the leads on the bottom surface of the package to the pcb. as a result, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. a copper (cu) fill is to be designed into the pcb as a thermal pad under the package. heat is transferred from the fx1 through the device?s metal paddle on the bottom side of the package. heat from here, is conducted to the pcb at the thermal pad. it is then conducted from the thermal pad to the pcb inner ground plane by a 5 5 array of via. a via is a plated through hole in the pcb with a finished diameter of 13 mil. the qfn?s metal die paddle must be soldered to the pcb?s thermal pad. solder mask is placed on the board top side over each via to resist solder flow into the via. the mask on the top side also minimizes outgassing during the solder reflow process. for further information on this package design please refer to ?application notes for surface mount assembly of amkor's microleadframe (mlf) packages?. this can be found on amkor's website http://www.amkor.com . the application note provides detailed information on board mounting guidelines, soldering flow, rework process, and so on. figure 40 on page 69 displays a cross-sectional area underneath the package. the cross section is of only one via. the solder paste template needs to be designed to allow at least 50% solder coverage. the thickness of the solder paste template must be 5 mil. it is recommended that ?no clean? type 3 solder paste is used for mounting the part. nitrogen purge is recommended during reflow. figure 41 on page 69 is a plot of the solder mask pattern and figure 42 on page 69 displays an x-ray image of the assembly (darker areas indicate solder). 51-85101 *f
cy7c64713 document number: 38-08039 rev. *l page 69 of 74 figure 40. cross section of the area underneath the qfn package figure 41. plot of the solder mask (white area) figure 42. x-ray image of the assembly 0.017? dia solder mask cu fill cu fill pcb material pcb material 0.013? dia via hole for thermally connecting the qfn to the circuit board ground plane. this figure only shows the top three layers of the circuit board: top solder, pcb dielectric, and the ground plane.
cy7c64713 document number: 38-08039 rev. *l page 70 of 74 acronyms document conventions units of measure acronym description asic application specific integrated circuit ata advanced technology attachment cpu central processing unit did device identifier dsl digital service line dsp digital signal processor ecc error correction code eeprom electrically erasable programmable read-only memory epp enhanced parallel port fifo first in first out gpif general programmable interface gpio general purpose input/output i/o input/output lan local area network lsb least significant bit msb most significant bit pcb printed circuit board pcmcia personal computer me mory card international association pid product identifier pll phase-locked loop qfn quad flat no leads ram random access memory sfr special function register sie serial interface engine sof start of frame ssop shrink small-outline package tqfp thin quad flat pack usarts universal serial asynch ronous receiver/transmitter usb universal serial bus utopia universal test and operations physical-layer interface vid vendor identifier symbol unit of measure cm centi meter c degree celsius khz kilo hertz k ? kilo ohms mbps mega bits per second mbps mega bytes per second mhz mega hertz a micro amperes s micro seconds w micro watts ma milli amperes mm milli meter ms milli seconds mw milli watts ns nano seconds ? ohms ppm parts per million % percent pf pico farad vvolts
cy7c64713 document number: 38-08039 rev. *l page 71 of 74 errata this section describes the errata for the ez-usb fx1/cy7c64713/ 4. details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. contact your local cypress sales representative if you have further questions. part numbers affected ez-usb fx1 qualification status in production ez-usb fx1 errata summary the following table defines the errata applicabili ty to available ez-usb fx1? family devices. 1. empty flag assertion problem definition when configured in slave fifo asynchronous word wide mode and if only single word data transferred from usb host to ep2 configured as out end point (ep) in the very first transaction then empty flag behaves incorrectly. this does not happened if d ata size is more than a word length in the first transaction. parameters affected na trigger condition(s) in slave fifo word wide mode, after firmware boot and initializa tion, ep2 out endpoint empty flag indicates status as empty. upon data reception in ep2 it changes to not-empty. but if data transferred to ep2 is single word only, then asserting slrd wit h fifoadr pointing to any other endpoint, changes not-empty status to empty for ep2 even though a word data is there (or it is untouched) in ep2. this is noticed only when the single word is sent as the very first transa ction and does not happen if it fo llows multi-word packet as the first transaction. scope of impact external interface does not see data available in ep2 out endpoint and might end up waiting for data to be read. workaround any one of the following workaround can be used i.give out pulse signal to the slwr pin, with fifoadr pins poin ting to an endpoint other than ep2, after firmware initializatio n and before/after transferring the data to ep2 from host, or ii.set length of very first data to ep2 to be more than a word, or iii.prioritize ep2 read from master in case of mu ltiple out eps and single word write to ep2, or iv.write to any in ep, if any, from master before reading from other out eps (other than ep2) from master. fix status there is no silicon fix planned for this currently, you can use above workaround. part number device characteristics operating range cy7c64713/4 all commercial items part number silicon revision fix status [1]. empty flag assertion cy7c64713/4 b no silicon fix planned currently. use workaround
cy7c64713 document number: 38-08039 rev. *l page 72 of 74 document history page document title: cy7c64713, ez-usb fx1? usb micr ocontroller full speed usb peripheral controller document number: 38-08039 revision ecn orig. of change submission date description of change ** 132091 kku 02/10/04 new data sheet. *a 230709 kku see ecn changed lead free marketing part numbers in ordering information according to spec change in 28-00054. *b 307474 bha see ecn changed default pid in table 2 on page 5 . updated register table. removed word compatible where associated with i2c. changed set-up to setup. added power dissipation. changed vcc from 10% to 5% added values for v ih_x , v il_x added values for i cc added values for i susp removed i unconfigured from dc characteristics on page 47 . changed pktend to flags output propagation delay (asynchronous interface) in table 10-14 from a maximum value of 70 ns to 115 ns. removed 56 ssop and added 56 qfn package. provided additional timing restrictions and requirement re garding the use of pktend pin to commit a short one byte /word packet subsequent to committing a packet automatically (when in auto mode). added part number cy7c64714 ideal for battery powered applications. changed supply voltage in section 8 to read +3.15v to +3.45v. added min vcc ramp up time (0 to 3.3 v). removed preliminary. *c 392702 bha see ecn corrected signal name for pin 54 in figure 10 on page 18 . added information on the autoptr1/autoptr2 address timing with regards to data memory read/write timing diagram. removed tbd in table 15 on page 53 . added section portc strobe feature timings on page 51 . *d 1664787 cmcc/ jasm see ecn added the 56 pin ssop pinout and package information. delete cy7c64714. *e 2088446 jasm see ecn updated package diagrams. *f 2710327 dpt 05/22/2009 added 56-pin qfn (8 8 mm) package diagram updated ordering information for CY7C64713-56LTXC part *g 2765406 odc 09/17/2009 added pb-free for the cy7c64 713-56ltxc part in the ordering information table. updated 56-pin sawn qfn package diagram. *h 2896318 odc 03/18/2010 removed obsolete part cy 7c64713-56lfxc. updated all package diagrams. *i 3186891 odc 03/03/2011 template updates. updated package diagrams: 51-85144 , 51-85050, 51-85101 *j 3259101 odc 05/17/2011 added ordering code definitions . updated package diagrams . added acronyms and units of measure . updated in new template.
cy7c64713 document number: 38-08039 rev. *l page 73 of 74 *k 3999873 sirk 07/22/2013 added errata footnote (note 3). updated functional overview : updated interrupt system : updated fifo/gpif interrupt (int4) : added note 3 and referred the same note in ?endpoint 2 empty flag? in table 4 . updated package diagrams : spec 51-85062 ? changed revision from *d to *f. spec 001-53450 ? changed revision from *b to *c. added errata . updated in new template. *l 4302739 dbir 03/09/2014 updated package diagrams : spec 001-53450 ? changed revision from *c to *d. spec 51-85050 ? changed revision from *d to *e. spec 51-85101 ? changed revision from *e to *f. completing sunset review. document history page (continued) document title: cy7c64713, ez-usb fx1? usb micr ocontroller full speed usb peripheral controller document number: 38-08039 revision ecn orig. of change submission date description of change
document number: 38-08039 rev. *l revised march 9, 2014 page 74 of 74 ez-usb fx1, ez-usb fx2lp, ez-usb fx2, and renumeration are trademarks, and ez-usb is a registered trademark, of cypress semicon ductor. all product and company names mentioned in this document are the trademarks of their respective holders. cy7c64713 ? cypress semiconductor corporation, 2004-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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